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21 条记录 (耗时 0.04 秒)

    Latency control circuit and method using queuing design method
    12.
    发明授权
    Latency control circuit and method using queuing design method 失效
    延迟控制电路和使用排队设计方法的方法

    公开(公告)号：US08230140B2

    公开(公告)日：2012-07-24

    申请号：US13178846

    申请日：2011-07-08

    申请人： Byung-Hoon Jeong ,  Hoe-Ju Chung

    发明人： Byung-Hoon Jeong ,  Hoe-Ju Chung

    IPC分类号： G06F3/00

    CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/109 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272

    摘要： A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

    摘要翻译： 等待时间控制电路包括FIFO控制器和寄存器单元。 FIFO控制器可以根据外部命令生成增加信号，并根据内部命令生成减少信号。 FIFO控制器还可以响应于增加信号和减小信号启用深度点信号。 寄存器单元可以包括n个寄存器。 值n（四舍五入）可以通过将最大数量的加性延迟和最大写入延迟数的较大值除以列周期延迟时间（tCCD）来获得。 寄存器可以响应于增加信号和时钟信号而存储与外部命令接收的地址，并且可以将地址或先前地址移位到相邻寄存器。 延迟控制电路将存储在寄存器中的地址作为与启用的深度点信号相对应的列地址。

    Internal signal replication device and method
    13.
    发明授权
    Internal signal replication device and method 失效
    内部信号复制设备及方法

    公开(公告)号：US07242232B2

    公开(公告)日：2007-07-10

    申请号：US11126428

    申请日：2005-05-10

    申请人： Chul-Soo Kim ,  Byung-Hoon Jeong

    发明人： Chul-Soo Kim ,  Byung-Hoon Jeong

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222

    摘要： We describe and claim an internal signal replication device and method. A circuit comprising a selector to select one of a plurality of internally generated clock signals, and a compensation circuit to replicate the selected clock signal from a reference clock signal.

    摘要翻译： 我们描述并声明内部信号复制设备和方法。 一种电路，包括选择器以选择多个内部产生的时钟信号中的一个，以及补偿电路，以从参考时钟信号复制所选择的时钟信号。

    Shared decoupling capacitance
    14.
    发明授权
    Shared decoupling capacitance 有权
    共享去耦电容

    公开(公告)号：US07110316B2

    公开(公告)日：2006-09-19

    申请号：US10951053

    申请日：2004-09-27

    申请人： Hyung-Chan Choi ,  Chi-Wook Kim ,  Byung-Hoon Jeong

    发明人： Hyung-Chan Choi ,  Chi-Wook Kim ,  Byung-Hoon Jeong

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147 ,  G11C5/14

    摘要： Decoupling capacitance of at least one shared capacitor is distributed among a plurality of voltage sources for enhanced performance with minimized area of a semiconductor device. The high nodes and the low nodes of such voltage sources each comprise at least two distinct nodes for lower noise at the voltage sources. The present invention is applied to particular advantage for coupling a variable number of shared capacitors to a data charge voltage source depending on a bit organization of the semiconductor device.

    摘要翻译： 至少一个共享电容器的去耦电容分布在多个电压源之间，以便在半导体器件的面积最小的情况下提高性能。 这些电压源的高节点和低节点各自包括至少两个不同的节点，用于在电压源处降低噪声。 本发明应用于根据半导体器件的位组织将可变数量的共享电容器耦合到数据充电电压源的特别优点。

    Circuit and method for controlling inversion of delay locked loop and delay locked loop and synchronous semiconductor memory device using the same
    16.
    发明申请
    Circuit and method for controlling inversion of delay locked loop and delay locked loop and synchronous semiconductor memory device using the same 失效
    用于控制延迟锁定环和延迟锁定环的反相的电路和方法及使用其的同步半导体存储器件

    公开(公告)号：US20050141334A1

    公开(公告)日：2005-06-30

    申请号：US11000940

    申请日：2004-12-02

    申请人： Byung-Hoon Jeong

    发明人： Byung-Hoon Jeong

    IPC分类号： G11C8/00 ,  G11C7/22 ,  G11C29/02

    CPC分类号： G11C29/028 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/50012

    摘要： A Delayed Lock Loop (DLL) circuit includes an inversion control circuit. The inversion control circuit includes an inversion decision circuit to determine the inversion of reproduction clock signal by comparing phases of an external clock signal and a reproduction clock signal, and to produce an inversion decision signal including a duty error margin for the reproduction clock signal. The inversion control circuit also includes an output latch to latch the inversion decision signal in synchronization with a start signal to produce an inversion control signal.

    摘要翻译： 延迟锁定环路（DLL）电路包括一个反相控制电路。 反转控制电路包括：反相判定电路，用于通过比较外部时钟信号和再现时钟信号的相位来确定再现时钟信号的反相，并产生包括再现时钟信号的占空比误差余量的反转判定信号。 反相控制电路还包括输出锁存器，以与起始信号同步地锁存反相判定信号以产生反转控制信号。

    Delay-locked loop, integrated circuit having the same, and method of driving the same
    17.
    发明授权
    Delay-locked loop, integrated circuit having the same, and method of driving the same 失效
    延迟锁定环，具有相同的集成电路及其驱动方法

    公开(公告)号：US07336559B2

    公开(公告)日：2008-02-26

    申请号：US11730793

    申请日：2007-04-04

    申请人： Byung-Hoon Jeong

    发明人： Byung-Hoon Jeong

    IPC分类号： G11C8/00 ,  G11C8/18 ,  H03L7/06 ,  H03K7/08

    CPC分类号： G11C29/028 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/50012

    摘要： A delay-locked loop (DLL) is disclosed with a phase detector configured to detect a phase difference between an external clock signal and an internal clock signal, a variable delay line configured to variably delay the external clock signal in relation to the phase difference to generate an intermediate clock signal, a selection unit configured to select between the intermediate clock signal and an inverted version of the intermediate clock signal in relation to an inversion control signal, and to generate an internal clock signal according to the selection, and an inversion determination unit configured to generate the inversion control signal in relation to transition of the external clock signal within a duty error margin.

    摘要翻译： 延迟锁定环（DLL）被公开，相位检测器被配置为检测外部时钟信号和内部时钟信号之间的相位差，可变延迟线被配置为相对于相位差可变地延迟外部时钟信号 产生中间时钟信号，选择单元，被配置为在中间时钟信号和中间时钟信号的反相版本之间相对于反相控制信号进行选择，并根据该选择产生内部时钟信号，并且反演确定 被配置为在占空比误差容限内产生与外部时钟信号的转变相关的反相控制信号。

    SEMICONDUCTOR MEMORY DEVICE CORRECTING FUSE DATA AND METHOD OF OPERATING THE SAME
    18.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE CORRECTING FUSE DATA AND METHOD OF OPERATING THE SAME 有权
    修正保险丝数据的半导体存储器件及其操作方法

    公开(公告)号：US20120188830A1

    公开(公告)日：2012-07-26

    申请号：US13281762

    申请日：2011-10-26

    申请人： Byung-Hoon Jeong

    发明人： Byung-Hoon Jeong

    IPC分类号： G11C29/52

    CPC分类号： G11C17/16 ,  G11C7/20 ,  G11C2029/0411

    摘要： A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data associated with the first fuse data, and an ECC decoder configured to generate second fuse data by correcting the first fuse data using the ECC data.

    摘要翻译： 描述半导体存储器件及其操作方法。 半导体存储器件包括具有存储第一熔丝数据的多个第一反熔丝元件的第一反熔丝阵列，具有存储纠错码（ECC）数据的多个第二反熔丝元件的第二反熔丝阵列 与ECC解码器配置成通过使用ECC数据校正第一熔丝数据来生成第二熔丝数据。

    Repair circuit and method of repairing defects in a semiconductor memory device
    19.
    发明申请
    Repair circuit and method of repairing defects in a semiconductor memory device 有权
    维修电路及修复半导体存储器件缺陷的方法

    公开(公告)号：US20070133323A1

    公开(公告)日：2007-06-14

    申请号：US11604700

    申请日：2006-11-28

    申请人： Hyung-Jik Kim ,  Byung-Hoon Jeong

    发明人： Hyung-Jik Kim ,  Byung-Hoon Jeong

    IPC分类号： G11C29/00

    CPC分类号： G11C29/789 ,  G11C7/24

    摘要： A repair circuit and a method of repairing defects in a semiconductor memory device are disclosed. The repair circuit of a semiconductor memory device includes an address generating unit, an address electrical fuse (e-fuse) box unit, a row/column selecting e-fuse unit, a row repair control unit, and a column repair control unit. The address generating unit generates a row address or a column address in response to a control signal, the address e-fuse box unit stores a defective address after packaging, and the row/column selecting e-fuse unit generates a select signal for determining whether the defective address corresponds to a row defect or a column defect. The row repair control unit compares the defective address after packaging with the row address in response to a first state of the select signal, and the column repair control unit compares the defective address after packaging with the column address in response to a second state of the select signal.

    摘要翻译： 公开了修复电路和修复半导体存储器件中的缺陷的方法。 半导体存储器件的修复电路包括地址产生单元，地址电熔丝（e-fuse）盒单元，行/列选择电熔丝单元，行修理控制单元和列修复控制单元。 地址生成单元响应于控制信号生成行地址或列地址，地址电子保险箱单元存储打包后的缺陷地址，行/列选择电子熔丝单元生成用于确定是否 缺陷地址对应于行缺陷或列缺陷。 行修复控制单元响应于选择信号的第一状态将包装后的缺陷地址与行地址进行比较，并且列修复控制单元响应于第二状态来比较打包后的缺陷地址与列地址 选择信号。

    Circuit and method for controlling inversion of delay locked loop and delay locked loop and synchronous semiconductor memory device using the same
    20.
    发明授权
    Circuit and method for controlling inversion of delay locked loop and delay locked loop and synchronous semiconductor memory device using the same 失效
    用于控制延迟锁定环和延迟锁定环的反相的电路和方法以及使用其的同步半导体存储器件

    公开(公告)号：US07215596B2

    公开(公告)日：2007-05-08

    申请号：US11000940

    申请日：2004-12-02

    申请人： Byung-Hoon Jeong

    发明人： Byung-Hoon Jeong

    IPC分类号： G11C8/00 ,  G11C8/18 ,  H03L7/06 ,  H03K7/08

    CPC分类号： G11C29/028 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/50012

    摘要： A Delayed Lock Loop (DLL) circuit includes an inversion control circuit. The inversion control circuit includes an inversion decision circuit to determine the inversion of reproduction clock signal by comparing phases of an external clock signal and a reproduction clock signal, and to produce an inversion decision signal including a duty error margin for the reproduction clock signal. The inversion control circuit also includes an output latch to latch the inversion decision signal in synchronization with a start signal to produce an inversion control signal.

    摘要翻译： 延迟锁定环路（DLL）电路包括一个反相控制电路。 反转控制电路包括：反相判定电路，用于通过比较外部时钟信号和再现时钟信号的相位来确定再现时钟信号的反相，并产生包括再现时钟信号的占空比误差余量的反转判定信号。 反相控制电路还包括输出锁存器，以与起始信号同步地锁存反相判定信号以产生反转控制信号。