公开(公告)号：US06258730B1

公开(公告)日：2001-07-10

申请号：US09246462

申请日：1999-02-09

申请人： Sey-Ping Sun ,  Mark I. Gardner ,  Shengnian Song

发明人： Sey-Ping Sun ,  Mark I. Gardner ,  Shengnian Song

IPC分类号： H01L2131

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28211 ,  H01L21/31662

摘要： A fabrication process for semiconductor devices is disclosed for forming ultra-thin gate oxides, whereby a silicon substrate is subjected to an N2O plasma to form the ultra-thin gate oxide. According to one embodiment, the silicon substrate is heated in a deposition chamber and the N2O plasma is created by applying RF power to a showerhead from which the N2O is dispensed. By reacting an N2O plasma directly with the silicon substrate it is possible to achieve gate oxides with thicknesses less than 20 Å and relative uniformities of less than 1% standard deviation. The oxide growth rate resulting from the presently disclosed N2O plasma treatment is much slower than other known oxide formation techniques. One advantage of the disclosed N2O plasma treatment over thermal oxidation lies in the predictability of oxide growth thickness resulting from reaction with N2O plasma versus the strong variation in oxide formation rates exhibited by thermal oxidation. Following gate oxide formation, a high temperature anneal may be performed, preferably in an RTA apparatus. By combining the N2O plasma treatment with an RTA process, the disclosed method is believed to offer a controllable and reproducible method for fabricating highly uniform, ultra-thin gate oxides, having low trapping state densities.

摘要翻译： 公开了用于形成超薄栅极氧化物的半导体器件的制造工艺，由此使硅衬底经受N 2 O等离子体以形成超薄栅极氧化物。 根据一个实施例，在沉积室中加热硅衬底，并且通过将RF功率施加到分配N2O的喷头来产生N 2 O等离子体。 通过使N2O等离子体直接与硅衬底反应，可以实现厚度小于20的栅极氧化物和小于1％标准偏差的相对均匀性。 由本发明的N2O等离子体处理产生的氧化物生长速度比其它已知的氧化物形成技术慢得多。 所公开的N2O等离子体处理对热氧化的一个优点在于与N2O等离子体反应产生的氧化物生长厚度与热氧化显示的氧化物形成速率的强烈变化的可预测性。 在形成栅极氧化物之后，可以优选在RTA装置中进行高温退火。 通过将N2O等离子体处理与RTA工艺结合，所公开的方法被认为是提供具有低陷阱状态密度的制造高度均匀的超薄栅极氧化物的可控和可再现的方法。

公开(公告)号：US06171917B2

公开(公告)日：2001-01-09

申请号：US09048192

申请日：1998-03-25

申请人： Sey-Ping Sun ,  Thomas E. Spikes ,  Fred N. Hause

发明人： Sey-Ping Sun ,  Thomas E. Spikes ,  Fred N. Hause

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/31116 ,  H01L21/3185 ,  H01L29/665

摘要： A method is provided for forming high quality nitride sidewall spacers laterally adjacent to the opposed sidewall surfaces of a gate conductor dielectrically spaced above a semiconductor substrate. In an embodiment, a polysilicon gate conductor is provided which is arranged between a pair of opposed sidewall surfaces upon a gate dielectric. The gate dielectric is arranged upon a semiconductor substrate. Nitride is deposited from a high density plasma source across exposed surfaces of the substrate and the gate conductor. The high density plasma source may be generated within an ECR or ICP reactor containing a gas bearing N2 and SiH4. The energy and flux of electrons, ions, and radicals within the plasma are strictly controlled by the magnetic field such that a substantially stoichiometric and contaminant-free nitride is deposited upon the semiconductor topography. Thereafter, the nitride is anisotropically etched so as to form nitride spacers laterally adjacent the sidewall surfaces of the gate conductor.

摘要翻译： 提供了一种用于在与半导体衬底上介电间隔的栅极导体的相对的侧壁表面横向相邻形成高质量氮化物侧壁间隔件的方法。 在一个实施例中，提供多晶硅栅极导体，其布置在栅极电介质上的一对相对的侧壁表面之间。 栅极电介质被布置在半导体衬底上。 氮化物从高密度等离子体源沉积在衬底和栅极导体的暴露表面上。 高密度等离子体源可以在含有气体N2和SiH4的ECR或ICP反应器内产生。 等离子体中的电子，离子和自由基的能量和通量被磁场严格控制，使得在半导体形貌上沉积基本上化学计量和无污染的氮化物。 此后，各向异性蚀刻氮化物，以便在栅极导体的侧壁表面侧向邻接形成氮化物间隔。

公开(公告)号：US6114219A

公开(公告)日：2000-09-05

申请号：US929865

申请日：1997-09-15

申请人： Thomas E. Spikes, Jr. ,  Sey-Ping Sun ,  Robert Dawson

发明人： Thomas E. Spikes, Jr. ,  Sey-Ping Sun ,  Robert Dawson

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： A method for the manufacture of a semiconductor device with trench isolation regions includes forming at least one trench in a substrate to define one or more isolation regions. At least a portion of the trench is filled with a flowable oxide-generating material which is then formed into an oxide layer. An optional dielectric layer can be deposited over the oxide layer. A portion of the oxide layer and/or the optional dielectric layer is removed to generate a substantially planer surface.

摘要翻译： 用于制造具有沟槽隔离区域的半导体器件的方法包括在衬底中形成至少一个沟槽以限定一个或多个隔离区域。 沟槽的至少一部分填充有可流动的氧化物生成材料，然后将其形成为氧化物层。 可以在氧化物层上沉积可选的介电层。 去除氧化物层和/或可选介电层的一部分以产生基本上平的表面。

公开(公告)号：US08946828B2

公开(公告)日：2015-02-03

申请号：US12702683

申请日：2010-02-09

申请人： Sey-Ping Sun ,  Tsung-Lin Lee ,  Chin-Hsiang Lin ,  Chih-Hao Chang ,  Chen-Nan Yeh ,  Chao-An Jong

发明人： Sey-Ping Sun ,  Tsung-Lin Lee ,  Chin-Hsiang Lin ,  Chih-Hao Chang ,  Chen-Nan Yeh ,  Chao-An Jong

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L29/4232 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

摘要： A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack.

摘要翻译： 半导体器件包括半导体衬底; 覆盖衬底的栅极堆叠，形成在栅极堆叠的侧壁上的间隔物，以及覆盖栅极堆叠的保护层，用于填充由间隔物和栅极堆叠的顶表面围绕的空间的至少一部分。 间隔件的顶表面高于栅极堆叠的顶表面。

公开(公告)号：US20110272791A1

公开(公告)日：2011-11-10

申请号：US13184050

申请日：2011-07-15

申请人： David E. Brown ,  Hans Van Meer ,  Sey-Ping Sun

发明人： David E. Brown ,  Hans Van Meer ,  Sey-Ping Sun

IPC分类号： H01L27/06 ,  H01L21/20

CPC分类号： H01L29/0684 ,  H01L21/84 ,  H01L27/1203

摘要： A method far farming different active thicknesses on the same silicon layer includes masking the silicon layer and exposing selected regions of the silicon layer. The thickness of the silicon layer at the exposed regions is changed, either by adding silicon or subtracting silicon from the layer at the exposed regions. Once the mask is removed, the silicon layer has regions of different active thicknesses, respectively suitable for use in different types of devices, such as diodes and transistors.

摘要翻译： 在同一硅层上种植不同有源厚度的方法包括掩蔽硅层并暴露硅层的选定区域。 通过在曝光区域从层中添加硅或从中减去硅来改变暴露区域处的硅层的厚度。 一旦去除掩模，硅层就具有不同有源厚度的区域，分别适用于不同类型的器件，例如二极管和晶体管。

公开(公告)号：US20110193144A1

公开(公告)日：2011-08-11

申请号：US12702683

申请日：2010-02-09

申请人： Sey-Ping Sun ,  Tsung-Lin Lee ,  Chin-Hsiang Lin ,  Chih-Hao Chang ,  Chen-Nan Yeh ,  Chao-An Jong

发明人： Sey-Ping Sun ,  Tsung-Lin Lee ,  Chin-Hsiang Lin ,  Chih-Hao Chang ,  Chen-Nan Yeh ,  Chao-An Jong

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/4232 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

摘要： A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack.

摘要翻译： 半导体器件包括半导体衬底; 覆盖衬底的栅极堆叠，形成在栅极堆叠的侧壁上的间隔物，以及覆盖栅极堆叠的保护层，用于填充由间隔物和栅极堆叠的顶表面围绕的空间的至少一部分。 间隔件的顶表面高于栅极堆叠的顶表面。

公开(公告)号：US06492281B1

公开(公告)日：2002-12-10

申请号：US09668443

申请日：2000-09-22

申请人： Shengnian Song ,  Bradley Davis ,  Sey-Ping Sun

发明人： Shengnian Song ,  Bradley Davis ,  Sey-Ping Sun

IPC分类号： H01L21302

CPC分类号： H01L21/32051 ,  H01L21/76838

摘要： Various methods of inspecting a workpiece for residue are provided. In one aspect, a method of fabricating a conductor layer on a substrate is provided that includes forming an aluminum-copper film on the substrate in a first processing chamber and forming an anti-reflective coating on the aluminum-copper film in a second processing chamber. The substrate is moved from the second processing chamber into a cooling chamber to quench the substrate. A first time interval during which the substrate is in the first processing chamber and second time interval during which the substrate is present in the second processing chamber are measured. The substrate is annealed to restore a uniform equilibrium distribution of copper in the aluminum if the first time interval exceeds about 600 seconds or the second time interval exceeds about 300 seconds. The method substantially reduces the risk of metal comb bridging device failures following etch definition of conductor lines.

摘要翻译： 提供了检查残留物的各种方法。 一方面，提供一种在基板上制造导体层的方法，其包括在第一处理室中的基板上形成铝 - 铜膜，并在第二处理室中的铝 - 铜膜上形成抗反射涂层 。 将基板从第二处理室移动到冷却室中以淬火基板。 测量基板处于第一处理室的第一时间间隔和第二处理室中存在基板的第二时间间隔。 如果第一时间间隔超过约600秒或第二时间间隔超过约300秒，则将基板退火以恢复铝在铝中的均匀均匀分布。 该方法大大降低了导体线蚀刻定义后金属梳状桥接器件故障的风险。

公开(公告)号：US06383874B1

公开(公告)日：2002-05-07

申请号：US09800862

申请日：2001-03-07

申请人： Sey-Ping Sun ,  Mark I. Gardner ,  Robert W. Anderson

发明人： Sey-Ping Sun ,  Mark I. Gardner ,  Robert W. Anderson

IPC分类号： H01L21336

CPC分类号： H01L21/76224

摘要： A device stack for fabrication of an isolation structure and methods of fabricating the same are provided. In one aspect, a method of processing a substrate is provided that includes exposing the substrate to a plasma ambient containing nitrogen and oxygen to form a nitrogen containing interface. An oxide film is formed on the nitrogen containing interface and a silicon rich nitride film is formed on the oxide film. The silicon rich nitride film is exposed to a plasma ambient containing oxygen to convert an upper portion of the silicon rich nitride film to silicon oxynitride. The optical properties of the nitride film are enhanced so that UV lithographic patterning of etch masking is improved.

摘要翻译： 提供了用于制造隔离结构的器件堆叠及其制造方法。 在一个方面，提供了一种处理衬底的方法，其包括将衬底暴露于含有氮和氧的等离子体环境中以形成含氮界面。 在含氮界面上形成氧化膜，在氧化物膜上形成富含氮的氮化物膜。 富硅氮化物膜暴露于含有氧的等离子体环境，以将富硅氮化物膜的上部转化为氮氧化硅。 氮化膜的光学特性得到增强，从而提高了蚀刻掩模的UV光刻图案。

公开(公告)号：US06259133B1

公开(公告)日：2001-07-10

申请号：US09248432

申请日：1999-02-11

申请人： Mark I. Gardner ,  Sey-Ping Sun

发明人： Mark I. Gardner ,  Sey-Ping Sun

IPC分类号： H01L218247

CPC分类号： H01L27/11526 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11541 ,  H01L27/11551 ,  H01L29/42324 ,  H01L29/7883

摘要： A method for fabricating an integrated circuit is presented. In the method, a dielectric layer is formed, and then a conductive layer is formed upon the dielectric layer. A base gate may then be patterned from the conductive layer. An intergate dielectric is preferably formed over and around the base gate. A spacer gate may then be formed such that at least a portion of the spacer gate is elevationally below an upper portion of the base gate. At least a portion of the intergate dielectric layer is preferably interposed between a sidewall surface of the spacer gate and a sidewall surface of the base gate. The final memory cell fabricated in this manner does not need to transfer electrons from a semiconducting substrate during operation.

摘要翻译： 提出了一种用于制造集成电路的方法。 在该方法中，形成介电层，然后在电介质层上形成导电层。 然后可以从导电层图案化基栅。 优选地，在基栅上方和周围形成隔间电介质。 然后可以形成间隔栅，使得间隔栅的至少一部分在基栅的上部的正上方。 隔间电介质层的至少一部分优选插入在间隔栅极的侧壁表面和基栅的侧壁表面之间。 以这种方式制造的最终存储单元在操作期间不需要从半导体衬底传输电子。

公开(公告)号：US6150286A

公开(公告)日：2000-11-21

申请号：US477050

申请日：2000-01-03

申请人： Sey-Ping Sun ,  Mark I. Gardner ,  Shengnian Song

发明人： Sey-Ping Sun ,  Mark I. Gardner ,  Shengnian Song

IPC分类号： H01L21/28 ,  H01L21/318 ,  H01L29/51 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L29/518 ,  H01L21/3185 ,  Y10S438/958

摘要： Various methods of fabricating a circuit structure utilizing silicon nitride are provided. In one aspect, a method of fabricating a circuit structure is provided that includes forming a silicon nitride film on a silicon surface, annealing the silicon nitride film in an ammonia ambient and annealing the silicon nitride film in a nitrous oxide ambient to form a thin oxide layer at an interface between the silicon nitride film and the silicon surface. The process of the present invention enables the manufacture of thin silicon nitride films with highly uniform morphology for use as gate dielectrics or other purposes. The thin oxide film is self-limiting in thickness and improves differential mechanical stresses.

摘要翻译： 提供了使用氮化硅制造电路结构的各种方法。 一方面，提供一种制造电路结构的方法，其包括在硅表面上形成氮化硅膜，在氮气环境中退火氮化硅膜，并在氮氧化物环境中退火氮化硅膜以形成薄氧化物 在氮化硅膜和硅表面之间的界面处。 本发明的方法能够制造具有高度均匀形态的薄氮化硅膜用作栅极电介质或其它目的。 薄氧化膜的厚度是自限制的，并且改善了不同的机械应力。