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    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby
    11.
    发明申请
    Process for manufacturing a phase change memory array in Cu-damascene technology and phase change memory array manufactured thereby 有权
    用于制造Cu-镶嵌技术中的相变存储器阵列的方法和由其制造的相变存储器阵列

    公开(公告)号：US20050064606A1

    公开(公告)日：2005-03-24

    申请号：US10902508

    申请日：2004-07-29

    申请人： Fabio Pellizzer ,  Roberto Bez

    发明人： Fabio Pellizzer ,  Roberto Bez

    IPC分类号： H01L27/24 ,  H01L21/00

    CPC分类号： H01L27/2472 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    摘要： A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells, arranged in rows and columns; and forming a plurality of resistive bit lines for connecting PCM cells arranged on a same column, each resistive bit lines comprising a respective phase change material portion, covered by a respective barrier portion. After forming the resistive bit lines, electrical connection structures for the resistive bit lines are formed directly in contact with the barrier portions of the resistive bit lines.

    摘要翻译： 一种制造相变存储器阵列的方法，包括以下步骤：形成以行和列排列的多个PCM单元; 以及形成用于连接布置在同一列上的PCM单元的多个电阻位线，每个电阻位线包括由相应的阻挡部分覆盖的各个相变材料部分。 在形成电阻位线之后，电阻位线的电连接结构直接形成为与电阻位线的势垒部分接触。

    Field programmable gate array device
    12.
    发明申请
    Field programmable gate array device 有权
    现场可编程门阵列器件

    公开(公告)号：US20050062497A1

    公开(公告)日：2005-03-24

    申请号：US10948079

    申请日：2004-09-23

    申请人： Fabio Pellizzer ,  Guido De Sandre ,  Roberto Bez

    发明人： Fabio Pellizzer ,  Guido De Sandre ,  Roberto Bez

    IPC分类号： G11C16/02 ,  G11C16/04 ,  H03K3/037 ,  H03K19/177

    CPC分类号： G11C13/0004 ,  G11C16/0416 ,  H03K3/0375 ,  H03K19/1776

    摘要： The present invention proposes a Field Programmable Gate Array device comprising a plurality of configurable electrical connections, a plurality of controlled switches, each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit including an arrangement of a plurality of control cells. Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

    摘要翻译： 本发明提出了一种现场可编程门阵列器件，其包括多个可配置的电连接，多个受控开关，每个控制开关适于响应于开关控制信号激活/去激活至少一个相应的电连接，控制单元 包括多个控制单元的布置。 每个控制单元通过相应的开关控制信号控制所述受控开关中的至少一个，每个控制单元包括易失性存储元件，其适于以易失性方式存储对应于至少一个受控开关的预选状态的控制逻辑值， 以及向受控开关提供与所存储的逻辑值对应的所述开关控制信号。 每个控制单元还包括耦合到易失性存储元件的非易失性存储元件，非易失性存储元件适于以非易失性方式存储控制逻辑值。

    Memory device
    13.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US06567296B1

    公开(公告)日：2003-05-20

    申请号：US10041684

    申请日：2001-10-24

    申请人： Giulio Casagrande ,  Tyler Lowrey ,  Roberto Bez ,  Guy Wicker ,  Edward Spall ,  Stephen Hudgens ,  Wolodymyr Czubatyj

    发明人： Giulio Casagrande ,  Tyler Lowrey ,  Roberto Bez ,  Guy Wicker ,  Edward Spall ,  Stephen Hudgens ,  Wolodymyr Czubatyj

    IPC分类号： G11C1706

    CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72

    摘要： A memory device including a plurality of memory cells, a plurality of insulated first regions of a first type of conductivity formed in a chip of semiconductor material, at least one second region of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements without interposition of any contact, and the memory device further includes means for forward biasing the access elements of each sub-set simultaneously.

    摘要翻译： 一种存储器件，包括多个存储器单元，形成在半导体材料的芯片中的第一类型的导电性的多个绝缘的第一区域，在每个第一区域中形成的至少一个第二导电类型的第二区域， 每个第二区域和相应的第一区域限定单向传导访问元件，用于当正向偏置时选择连接到第二区域的对应的存储单元，以及用于接触每个第一区域的至少一个触点; 在每个第一区域中形成多个访问元件，所述访问元件被分组成由多个相邻的访问元件组成的至少一个子集，而不插入任何联系人，并且所述存储器设备还包括： 每个子集的元素同时进行。

    Field programmable gate array device
    15.
    发明授权
    Field programmable gate array device 有权
    现场可编程门阵列器件

    公开(公告)号：US07307451B2

    公开(公告)日：2007-12-11

    申请号：US10948079

    申请日：2004-09-23

    申请人： Fabio Pellizzer ,  Guido De Sandre ,  Roberto Bez

    发明人： Fabio Pellizzer ,  Guido De Sandre ,  Roberto Bez

    IPC分类号： H03K19/177 ,  G11C11/34

    CPC分类号： G11C13/0004 ,  G11C16/0416 ,  H03K3/0375 ,  H03K19/1776

    摘要： The present invention proposes a Field Programmable Gate Array device comprising a plurality of configurable electrical connections, a plurality of controlled switches, each one adapted to activating/de-activating at least one respective electrical connection in response to a switch control signal and a control unit including an arrangement of a plurality of control cells. Each control cells controls at least one of said controlled switches by the respective switch control signal, each control cell including a volatile storage element adapted to storing in a volatile way a control logic value corresponding to a preselected status of the at least one controlled switch, and providing to the controlled switch said switch control signal corresponding to the stored logic value. Each control cell further includes a non-volatile storage element coupled to the volatile storage element, the non-volatile storage element being adapted to storing in a non-volatile way the control logic value.

    摘要翻译： 本发明提出了一种现场可编程门阵列器件，其包括多个可配置的电连接，多个受控开关，每个控制开关适于响应于开关控制信号激活/去激活至少一个相应的电连接，控制单元 包括多个控制单元的布置。 每个控制单元通过相应的开关控制信号控制所述受控开关中的至少一个，每个控制单元包括易失性存储元件，其适于以易失性方式存储对应于至少一个受控开关的预选状态的控制逻辑值， 以及向受控开关提供与所存储的逻辑值对应的所述开关控制信号。 每个控制单元还包括耦合到易失性存储元件的非易失性存储元件，非易失性存储元件适于以非易失性方式存储控制逻辑值。

    Phase change memory cell and manufacturing method thereof using minitrenches
    17.
    发明申请
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    相变存储单元及其制造方法

    公开(公告)号：US20050152208A1

    公开(公告)日：2005-07-14

    申请号：US11045170

    申请日：2005-01-27

    申请人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

    发明人： Roberto Bez ,  Fabio Pellizzer ,  Marina Tosi ,  Romina Zonca

    IPC分类号： G11C11/56 ,  H01L27/24 ,  H01L45/00 ,  G01R31/08

    CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    摘要： A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction; and the memory region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first thin portion and the second thin portion are in direct electrical contact and define a contact area of sublithographic extension. The second thin portion is delimited laterally by oxide spacer portions surrounded by a mold layer which defines a lithographic opening. The spacer portions are formed after forming the lithographic opening, by a spacer formation technique.

    摘要翻译： 一种方法使用电阻元件和相变材料的存储区形成相变存储单元。 电阻元件具有在第一方向上具有第一亚光刻尺寸的第一薄部分; 并且所述存储区域具有第二薄部分，所述第二薄部分具有横向于所述第一尺寸的第二方向的第二亚光刻尺寸。 第一薄部分和第二薄部分直接电接触并限定亚光刻延伸部分的接触面积。 第二薄部分被由限定光刻开口的模具层围绕的氧化物间隔部分侧向限定。 通过间隔物形成技术在形成光刻开口之后形成间隔部分。

    Memory arrays and methods of forming memory cells
    19.
    发明授权
    Memory arrays and methods of forming memory cells 有权

    公开(公告)号：US08546231B2

    公开(公告)日：2013-10-01

    申请号：US13298962

    申请日：2011-11-17

    申请人： Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

    发明人： Fabio Pellizzer ,  Roberto Bez ,  Lorenzo Fratin

    IPC分类号： G11C17/16

    CPC分类号： H01L45/1675 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/1683

    摘要： Some embodiments include methods of forming memory cells. A stack includes ovonic material over an electrically conductive region. The stack is patterned into rails that extend along a first direction. The rails are patterned into pillars. Electrically conductive lines are formed over the ovonic material. The electrically conductive lines extend along a second direction that intersects the first direction. The electrically conductive lines interconnect the pillars along the second direction. Some embodiments include a memory array having first electrically conductive lines extending along a first direction. The lines contain n-type doped regions of semiconductor material. Pillars are over the first conductive lines and contain mesas of the n-type doped regions together with p-type doped regions and ovonic material. Second electrically conductive lines are over the ovonic material and extend along a second direction that intersects the first direction. The second electrically conductive lines interconnect the pillars along the second direction.