公开(公告)号：US20190035919A1

公开(公告)日：2019-01-31

申请号：US15664418

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12 ,  H01L23/535 ,  H01L29/165 ,  H01L21/84 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L29/7378 ,  H01L21/02532 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/535 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66242

Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.

公开(公告)号：US10157777B2

公开(公告)日：2018-12-18

申请号：US15152797

申请日：2016-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Mark D. Jaffe ,  Randy L. Wolf ,  Alvin J. Joseph ,  Brett T. Cucci ,  Anthony K. Stamper

IPC: H01L29/00 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/84 ,  H01L23/66 ,  H01L29/786

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.

公开(公告)号：US09728603B2

公开(公告)日：2017-08-08

申请号：US14745764

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L29/00 ,  H01L29/08 ,  H01L29/73 ,  H01L29/66 ,  H01L29/737 ,  H01L29/06

CPC classification number: H01L29/0813 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/73 ,  H01L29/7371 ,  H01L29/7378

Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A base layer comprised of a first semiconductor material is formed. An emitter layer comprised of a second semiconductor material is formed on the base layer. The emitter layer is patterned to form an emitter finger having a length and a width that changes along the length of the emitter finger.

公开(公告)号：US10439053B2

公开(公告)日：2019-10-08

申请号：US16394421

申请日：2019-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L27/12 ,  H01L23/535 ,  H01L21/768 ,  H01L21/02 ,  H01L21/84

Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.

公开(公告)号：US20190267304A1

公开(公告)日：2019-08-29

申请号：US16405325

申请日：2019-05-07

Applicant: GlobalFoundries Inc.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L23/367 ,  H01L29/732 ,  H01L29/66 ,  H01L29/08 ,  H01L21/48 ,  H01L29/417

Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.

公开(公告)号：US10367084B2

公开(公告)日：2019-07-30

申请号：US15664418

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Qizhi Liu

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L27/12 ,  H01L23/535 ,  H01L21/02 ,  H01L21/768 ,  H01L21/84 ,  H01L29/165

Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.

公开(公告)号：US10367083B2

公开(公告)日：2019-07-30

申请号：US15081443

申请日：2016-03-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik ,  Alvin J. Joseph ,  Peter B. Gray

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417 ,  H01L21/762 ,  H01L29/73

Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.

公开(公告)号：US20190181250A1

公开(公告)日：2019-06-13

申请号：US16278268

申请日：2019-02-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Renata Camillo-Castillo ,  Qizhi Liu ,  John J. Pekarik ,  Alvin J. Joseph ,  Peter B. Gray

IPC: H01L29/732 ,  H01L29/08 ,  H01L21/762 ,  H01L29/417 ,  H01L29/73 ,  H01L29/10 ,  H01L29/06

Abstract: Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation regions are formed that surround an active device region of the substrate and a collector contact region of the substrate. A base layer is formed on the active device region and the collector contact region, and the active device region includes a collector. Each primary trench isolation region extends vertically to a first depth into the substrate. A trench is formed laterally located between the base layer and the collector contact region and that extends vertically through the base layer and into the substrate to a second depth that is less than the first depth. A dielectric is formed in the trench to form a secondary trench isolation region. An emitter is formed on the base layer.

公开(公告)号：US20190081597A1

公开(公告)日：2019-03-14

申请号：US15701672

申请日：2017-09-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Alvin J. Joseph ,  John J. Pekarik

IPC: H03F1/22 ,  H01L27/07 ,  H01L27/06 ,  H01L27/12 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06

Abstract: Structures for a cascode integrated circuit and methods of forming such structures. A field-effect transistor of the structure includes a gate electrode finger, a first source/drain region, and a second source/drain region. A bipolar junction transistor of the structure includes a first terminal, a base layer with an intrinsic base portion arranged on the first terminal, and a second terminal that includes one or more fingers arranged on the intrinsic base portion of the base layer. The intrinsic base portion of the base layer is arranged in a vertical direction between the first terminal and the second terminal. The first source/drain region is coupled with the first terminal, and the first source/drain region at least partially surrounds the bipolar junction transistor.

公开(公告)号：US20170330832A1

公开(公告)日：2017-11-16

申请号：US15152794

申请日：2016-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Mark D. Jaffe ,  Randy L. Wolf ,  Alvin J. Joseph ,  Brett T. Cucci ,  Anthony K. Stamper

IPC: H01L23/522 ,  H01L23/66 ,  H01L23/528 ,  H01L27/12

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/4821 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/1203

Abstract: A semiconductor device may include a transistor gate in a device layer; an interconnect layer over the device layer; and an air gap extending through the interconnect layer to contact an upper surface of the transistor gate. The air gap provides a mechanism to reduce both on-resistance and off-capacitance for applications using SOI substrates such as radio frequency switches.