公开(公告)号：US20200066885A1

公开(公告)日：2020-02-27

申请号：US16106344

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Qizhi Liu ,  Pernell Dongmo

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/08

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer is arranged over the active region, and a semiconductor layer is arranged on the base layer. The semiconductor layer includes a stepped profile with a first section having a first width adjacent to the base layer and a second section having a second width that is less than the first width. An emitter is arranged on the second section of the semiconductor layer.

公开(公告)号：US10535551B2

公开(公告)日：2020-01-14

申请号：US15919744

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. Feilchenfeld ,  Vibhor Jain ,  Qizhi Liu

IPC: H01L21/762 ,  H01L27/08 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/868 ,  H01L29/872 ,  H01L29/16 ,  H01L29/161

Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p-and n-terminals formed in an i-region above a substrate.

公开(公告)号：US20190252530A1

公开(公告)日：2019-08-15

申请号：US16394421

申请日：2019-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Alvin J. Joseph ,  Qizhi Liu

IPC: H01L29/737 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66 ,  H01L21/84 ,  H01L29/08 ,  H01L23/535 ,  H01L27/12 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7378 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/76224 ,  H01L21/76264 ,  H01L21/76895 ,  H01L21/84 ,  H01L23/535 ,  H01L27/04 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/165 ,  H01L29/66242 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/7371

Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.

公开(公告)号：US10115810B2

公开(公告)日：2018-10-30

申请号：US15437168

申请日：2017-02-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  John J. Pekarik

IPC: H01L21/331 ,  H01L29/66 ,  H01L29/737 ,  H01L29/165

Abstract: Device structures and fabrication methods for a heterojunction bipolar transistor. A collector of the device structure has a top surface and a sidewall that is inclined relative to the top surface. The device structure further includes an emitter, an intrinsic base that has a first thickness, and an extrinsic base coupled with the intrinsic base. The extrinsic base has a lateral arrangement relative to the intrinsic base and relative to the emitter. The intrinsic base has a vertical arrangement between the emitter and the top surface of the collector. The sidewall of the collector extends laterally to undercut the extrinsic base. The extrinsic base has a second thickness that is greater than a first thickness of the intrinsic base.

公开(公告)号：US09608096B1

公开(公告)日：2017-03-28

申请号：US14874039

申请日：2015-10-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Qizhi Liu ,  Vibhor Jain ,  James W. Adkisson ,  David L. Harame

IPC: H01L29/49 ,  H01L29/732 ,  H01L21/762 ,  H01L29/66 ,  H01L21/225 ,  H01L21/02 ,  H01L29/04 ,  H01L29/06

CPC classification number: H01L29/732 ,  H01L21/76 ,  H01L21/762 ,  H01L29/0642 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7371

Abstract: Device structure and fabrication methods for a bipolar junction transistor. One or more trench isolation regions are formed in a substrate to define a device region having a first width. A protect layer is formed on a top surface of the one or more trench isolation regions and a top surface of the device region. An opening is formed in the protect layer. The opening is coincides with the top surface of the first device region and has a second width that is less than or equal to the first width of the first device region. A base layer is formed that has a first section on the device region inside the first opening and a second section on the protect layer.

公开(公告)号：US09576899B2

公开(公告)日：2017-02-21

申请号：US14746891

申请日：2015-06-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Qizhi Liu ,  Ian A. McCallum-Cook

IPC: H01L23/00 ,  H01L23/525

CPC classification number: H01L23/5256 ,  H01L21/7682 ,  H01L23/522 ,  H01L23/5329

Abstract: Electrical fuses and methods for forming an electrical fuse. A semiconductor substrate is implanted to define a modified region in the semiconductor substrate. Trenches that surround the modified region and that penetrate into the semiconductor substrate to a depth greater than a depth of the modified region are formed in the modified region so as to define a fuse link of the electrical fuse. The substrate is removed from beneath the fuse link with a selective etching process that removes the semiconductor substrate with a first etch rate that is higher than a second etch rate of the modified region.

Abstract translation: 电熔丝和形成电熔丝的方法。 植入半导体衬底以限定半导体衬底中的改性区域。 围绕改性区域并且穿透到半导体衬底中的深度大于修饰区域的深度的沟槽形成在修改区域中，以便限定电熔丝的熔断体。 通过选择性蚀刻工艺从熔丝链下方去除衬底，其以比修改区域的第二蚀刻速率高的第一蚀刻速率去除半导体衬底。

公开(公告)号：US20160372396A1

公开(公告)日：2016-12-22

申请号：US14745800

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L23/367 ,  H01L21/48 ,  H01L29/08 ,  H01L29/73 ,  H01L29/66

CPC classification number: H01L23/367 ,  H01L21/4882 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/66272 ,  H01L29/732

Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.

Abstract translation: 芯片封装和形成芯片封装的方法。 芯片封装包括功率放大器和构造成影响热能传输的热通路结构。 功率放大器包括第一发射器指状物和第二发射器指状物，其具有至少一个基于与热路径结构接近度选择的参数。

公开(公告)号：US20160104770A1

公开(公告)日：2016-04-14

申请号：US14968286

申请日：2015-12-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC: H01L29/08 ,  H01L29/732

CPC classification number: H01L29/0826 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7325 ,  H01L29/7378

Abstract: Device structures for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.

Abstract translation: 双极结型晶体管的器件结构。 在衬底的顶表面上形成一层。 在该层中形成沟槽并且具有多个侧壁，其宽度在相对的一对侧壁之间的宽度随着距离衬底顶表面的距离的增加而变化。 在沟槽中形成双极结型晶体管的集电极基座。

公开(公告)号：US20160049503A1

公开(公告)日：2016-02-18

申请号：US14925690

申请日：2015-10-28

Applicant: Globalfoundries Inc.

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/04 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7371 ,  H01L21/7624 ,  H01L21/8249 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7325 ,  H01L2924/1305

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer.

Abstract translation: 双极结晶体管的制造方法，器件结构和设计结构。 形成与有源器件区域中的衬底的单晶半导体材料共同延伸的电介质结构。 形成半导体层，其包括与有源器件区域耦合的单晶部分。 半导体层具有与电介质结构的顶表面重叠的边缘。 在半导体层上形成本征基层。

公开(公告)号：US09219128B2

公开(公告)日：2015-12-22

申请号：US13800091

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC: H01L29/73 ,  H01L29/66 ,  H01L21/8249 ,  H01L29/732 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L21/762

CPC classification number: H01L29/7371 ,  H01L21/7624 ,  H01L21/8249 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7325 ,  H01L2924/1305

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer.

Abstract translation: 双极结晶体管的制造方法，器件结构和设计结构。 形成与有源器件区域中的衬底的单晶半导体材料共同延伸的电介质结构。 形成半导体层，其包括与有源器件区域耦合的单晶部分。 半导体层具有与电介质结构的顶表面重叠的边缘。 在半导体层上形成本征基层。