公开(公告)号：US07064064B2

公开(公告)日：2006-06-20

申请号：US11058783

申请日：2005-02-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

摘要翻译： 公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。 互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

公开(公告)号：US06975032B2

公开(公告)日：2005-12-13

申请号：US10319967

申请日：2002-12-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

公开(公告)号：US06399496B1

公开(公告)日：2002-06-04

申请号：US09714504

申请日：2000-11-16

申请人： Daniel Charles Edelstein ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Andrew H. Simon ,  Cyprian Emeka Uzoh

发明人： Daniel Charles Edelstein ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Andrew H. Simon ,  Cyprian Emeka Uzoh

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper conductor body and the electronic device for improving the electromigration resistance, the adhesion property and other surface properties of the interconnection structure. The present invention also discloses methods for forming an interconnection structure for providing electrical connections to an electronic device by first depositing a seed layer of copper alloy or other metal that does not contain copper on an electronic device, and then forming a copper conductor body on the seed layer intimately bonding to the layer such that electromigration resistance, adhesion and other surface properties of the interconnection structure are improved.

摘要翻译： 本发明公开了一种用于与电子设备进行电连接的互连结构，该电子设备包括基本上由铜形成的主体和不包含铜的铜合金或金属的籽晶层夹在铜导体本体和 用于提高互连结构的电迁移电阻，粘附性等表面性质的电子器件。 本发明还公开了用于形成互连结构的方法，该互连结构用于通过首先在电子器件上沉积铜合金或不含铜的其它金属的种子层，然后在其上形成铜导体，从而提供与电子器件的电连接 种子层紧密地结合到层上，使得互连结构的电迁移阻力，粘附性和其它表面性质得到改善。

公开(公告)号：US06181012B2

公开(公告)日：2001-01-30

申请号：US09067851

申请日：1998-04-27

申请人： Daniel Charles Edelstein ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Andrew H. Simon ,  Cyprian Emeka Uzoh

发明人： Daniel Charles Edelstein ,  James McKell Edwin Harper ,  Chao-Kun Hu ,  Andrew H. Simon ,  Cyprian Emeka Uzoh

IPC分类号： H01L23532

CPC分类号： H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper conductor body and the electronic device for improving the electromigration resistance, the adhesion property and other surface properties of the interconnection structure. The present invention also discloses, methods for forming an interconnection structure for providing electrical connections to an electronic device by first depositing a seed layer of copper alloy or other metal that does not contain copper on an electronic device, and then forming a copper conductor body on the seed layer intimately bonding to the layer such that electromigration resistance, adhesion and other surface properties of the interconnection structure are improved.

摘要翻译： 本发明公开了一种用于与电子设备进行电连接的互连结构，该电子设备包括基本上由铜形成的主体和不包含铜的铜合金或金属的籽晶层夹在铜导体本体和 用于提高互连结构的电迁移电阻，粘附性等表面性质的电子器件。 本发明还公开了用于形成用于提供与电子设备的电连接的互连结构的方法，该方法是首先在电子设备上沉积不含铜的铜合金或其他金属种子层，然后在铜 种子层紧密地结合到层上，使得互连结构的电迁移阻力，粘附性和其它表面性质得到改善。

公开(公告)号：US08823176B2

公开(公告)日：2014-09-02

申请号：US12247632

申请日：2008-10-08

申请人： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu ,  Surbhi Mittal

发明人： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu ,  Surbhi Mittal

IPC分类号： H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02

CPC分类号： H01L23/53238 ,  H01L21/02362 ,  H01L21/76849 ,  H01L21/76865 ,  H01L21/76868 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure including a noble metal-containing cap that is present at least on some portion of an upper surface of at least one conductive material that is embedded within an interconnect dielectric material is provided. In one embodiment, the noble metal-containing cap is discontinuous, e.g., exists as nuclei or islands on the surface of the at least one conductive material. In another embodiment, the noble metal-containing cap has a non-uniform thickness across the surface of the at least one conductive material.

摘要翻译： 提供一种互连结构，其包括至少存在于嵌入在互连电介质材料中的至少一种导电材料的上表面的至少一部分上的含贵金属的盖。 在一个实施方案中，含贵金属的帽是不连续的，例如以至少一种导电材料的表面上的核或岛状存在。 在另一个实施方案中，含贵金属的盖在至少一种导电材料的表面上具有不均匀的厚度。

公开(公告)号：US20110092031A1

公开(公告)日：2011-04-21

申请号：US12976445

申请日：2010-12-22

申请人： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu

发明人： Chih-Chao Yang ,  Lynne M. Gignac ,  Chao-Kun Hu

IPC分类号： H01L21/283

CPC分类号： H01L23/53295 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/5256 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer. As such, when current is provided to the fuse structure electromigration of the conductive material occurs and over time an opening is formed in the conductive material blowing the fuse element.

摘要翻译： 提供了一种半导体结构，其包括互连结构和位于相同互连级别内的不同区域中的熔丝结构。 互连结构具有高的电迁移率，而与互连结构相比，熔丝结构具有较低的电迁移电阻。 熔丝结构包括嵌入在互连电介质内的导电材料，其中导电材料的上表面具有存在于其中的高浓度的氧。 电介质覆盖层位于电介质材料和导电材料的顶部。 在导电材料和电介质覆盖层之间的界面处的表面氧化物层的存在降低了导电材料和电介质覆盖层之间的粘合性。 因此，当电流被提供给熔丝结构时，导电材料的电迁移发生，并且随着时间的推移，在引导熔丝元件的导电材料中形成开口。

公开(公告)号：US07439173B2

公开(公告)日：2008-10-21

申请号：US11869044

申请日：2007-10-09

申请人： Stephen E. Greco ,  Chao-Kun Hu ,  Paul S. McLaughlin

发明人： Stephen E. Greco ,  Chao-Kun Hu ,  Paul S. McLaughlin

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.

摘要翻译： 公开了一种具有增加的电迁移寿命和允许电流密度的集成电路及其形成方法。 在一个实施例中，集成电路包括连接到至少一个功能通孔的导线，以及至少一个虚拟通孔，其具有与导电线电连接的第一下端，以及电连接（隔离）至任何导电 线。 每个虚拟通孔从导电线垂直向上延伸，并且去除快速扩散路径的一部分，即金属到电介质盖界面，其被金属对金属衬垫界面代替。 因此，每个虚拟通孔可以减少金属扩散速率，从而增加电迁移寿命并允许增加电流密度。

公开(公告)号：US20080026567A1

公开(公告)日：2008-01-31

申请号：US11869044

申请日：2007-10-09

申请人： Stephen Greco ,  Chao-Kun Hu ,  Paul McLaughlin

发明人： Stephen Greco ,  Chao-Kun Hu ,  Paul McLaughlin

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.

摘要翻译： 公开了一种具有增加的电迁移寿命和允许电流密度的集成电路及其形成方法。 在一个实施例中，集成电路包括连接到至少一个功能通孔的导线，以及至少一个虚拟通孔，其具有与导电线电连接的第一下端，以及电连接（隔离）至任何导电 线。 每个虚拟通孔从导电线垂直向上延伸，并且去除快速扩散路径的一部分，即金属到电介质盖界面，其被金属对金属衬垫界面代替。 因此，每个虚拟通孔可以减少金属扩散速率，从而增加电迁移寿命并允许增加电流密度。

公开(公告)号：US06573606B2

公开(公告)日：2003-06-03

申请号：US09881444

申请日：2001-06-14

申请人： Carlos Juan Sambucetti ,  Xiaomeng Chen ,  Soon-Cheon Seo ,  Birenda Nath Agarwala ,  Chao-Kun Hu ,  Naftali Eliahu Lustig ,  Stephen Edward Greco

发明人： Carlos Juan Sambucetti ,  Xiaomeng Chen ,  Soon-Cheon Seo ,  Birenda Nath Agarwala ,  Chao-Kun Hu ,  Naftali Eliahu Lustig ,  Stephen Edward Greco

IPC分类号： H01L2144

CPC分类号： H01L23/53238 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A—X—Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.

摘要翻译： 在本发明中，提供了电隔离的铜互连结构界面，其涉及单个约50-300A厚的合金覆盖层，其控制互连部件的扩散和电迁移并且降低互连的整体有效介电常数; 封盖层被本领域中称为材料所包围的材料包围，其可以为随后的反应离子蚀刻操作提供抗蚀剂，并且还提供了在结构界面的制造中涉及无电沉积的相互依赖的工艺步骤。 本发明中的单层合金金属阻挡层是一般型AXY的合金，其中A是从钴（Co）和镍（Ni）中取出的金属，X是取自钨（W ），锡（Sn）和硅（Si），Y是从磷（P）和硼（B）取代的成员; 厚度在50至300埃的范围内。

公开(公告)号：US06448173B1

公开(公告)日：2002-09-10

申请号：US09589546

申请日：2000-06-07

申请人： Lawrence Alfred Clevenger ,  Ronald Gene Filippi ,  Kenneth Parker Rodbell ,  Roy Charles Iggulden ,  Chao-Kun Hu ,  Lynne Marie Gignac ,  Stefan Weber ,  Jeffrey Peter Gambino ,  Rainer Florian Schnabel

发明人： Lawrence Alfred Clevenger ,  Ronald Gene Filippi ,  Kenneth Parker Rodbell ,  Roy Charles Iggulden ,  Chao-Kun Hu ,  Lynne Marie Gignac ,  Stefan Weber ,  Jeffrey Peter Gambino ,  Rainer Florian Schnabel

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene process capable of reliably producing aluminum interconnects that exhibit improved electromigration characteristics over aluminum interconnects produced by conventional RIE techniques. In particular, the dual damascene process relies on a PVD-Ti/CVD-TiN barrier layer to produce aluminum lines that exhibit significantly reduced saturation resistance levels and/or suppressed electromigration, particularly in lines longer than 100 micrometers. The electromigration lifetime of the dual damascene aluminum line is strongly dependent on the materials and material fill process conditions. Significantly, deviations in materials and processing can result in electromigration lifetimes inferior to that achieved with aluminum RIE interconnects. In one example, current densities as high as 2.5 MA/cm2 are necessary to induce a statistically relevant number of fails due to electromigration.

摘要翻译： 一种能够可靠地生产铝互连的双镶嵌工艺，其通过常规RIE技术生产的铝互连件具有改善的电迁移特性。 特别地，双镶嵌工艺依赖于PVD-Ti / CVD-TiN阻挡层以产生显示出显着降低的饱和电阻水平和/或抑制电迁移的铝线，特别是在长于100微米的线中。 双镶嵌铝线的电迁移寿命很大程度上取决于材料和材料填充工艺条件。 重要的是，材料和加工的偏差可导致电迁移寿命低于铝RIE互连实现的寿命。 在一个示例中，高达2.5MA / cm 2的电流密度是诱导由于电迁移引起的统计上相关的失败数量所必需的。