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    Memory controllers
    11.
    发明授权
    Memory controllers 有权

    公开(公告)号：US09911490B2

    公开(公告)日：2018-03-06

    申请号：US15314687

    申请日：2014-05-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Ning Ge ,  Jianhua Yang ,  Frederick Perner ,  Janice H. Nickel

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2013/0045 ,  G11C2213/77

    Abstract: A memory controller includes a voltage control module that operates to isolate a target memristor of a memory crossbar array. The voltage control module applies a column voltage to a column line coupled to the target memristor, applies a first row voltage to all row lines not coupled to the target memristor and a second row voltage to a row line coupled to the target memristor, and senses a current through the target memristor to determine a state of the target memristor. The memory crossbar array includes a plurality of column lines, a plurality of row lines, a plurality of memristors, and a plurality of shorting switches. Each memristor is coupled between a unique combination of one column line and one row line. Each shorting switch has a high impedance resistor and a low impedance transistor, and each shorting switch is coupled to an end of a unique row line.

    Resistive elements to operate as a matrix of probabilities
    12.
    发明授权
    Resistive elements to operate as a matrix of probabilities 有权

    公开(公告)号：US09847124B2

    公开(公告)日：2017-12-19

    申请号：US15500500

    申请日：2015-04-23

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Miao Hu ,  John Paul Strachan ,  Ning Ge ,  Jianhua Yang

    IPC: G11C13/00 ,  G06N7/00 ,  G06F17/18

    CPC classification number: G11C13/0021 ,  G06F7/588 ,  G06F17/18 ,  G06G7/122 ,  G06N7/005

    Abstract: An example apparatus includes a crossbar array of signal lines and control lines. The example apparatus also includes an input controller in circuit with the control lines. The input control is to select one of the control lines. The example apparatus also includes first resistive elements connected between corresponding ones of the control lines and corresponding ones of the signal lines. The first resistive elements have first conductances set to operate as a matrix of probabilities that define a fixed transition kernel of a Markov Chain. The example apparatus also includes second resistive elements in circuit with the signal lines. The second resistive elements have second conductances set to select one of the signal lines exclusive of others of the signal lines based on a subset of the probabilities in the matrix of the probabilities.

    Nonvolatile memory cross-bar array
    18.
    发明授权
    Nonvolatile memory cross-bar array 有权

    公开(公告)号：US10319441B2

    公开(公告)日：2019-06-11

    申请号：US16220647

    申请日：2018-12-14

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Ning Ge ,  Jianhua Yang ,  John Paul Strachan ,  Miao Hu

    IPC: G11C13/04 ,  G11C13/00 ,  G06G7/16

    Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

    NONVOLATILE MEMORY CROSS-BAR ARRAY
    19.
    发明申请
    NONVOLATILE MEMORY CROSS-BAR ARRAY 审中-公开

    公开(公告)号：US20190139605A1

    公开(公告)日：2019-05-09

    申请号：US16220647

    申请日：2018-12-14

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Ning Ge ,  Jianhua Yang ,  John Paul Strachan ,  Miao Hu

    IPC: G11C13/00 ,  G06G7/16

    Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second sat of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

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