公开(公告)号：US07057259B2

公开(公告)日：2006-06-06

申请号：US10101337

申请日：2002-03-20

申请人： Tsunetoshi Arikado ,  Masao Iwase ,  Soichi Nadahara ,  Yuso Udo ,  Yukihiro Ushiku ,  Shinichi Nitta ,  Moriya Miyashita ,  Junji Sugamoto ,  Hiroaki Yamada ,  Hajime Nagano ,  Katsujiro Tanzawa ,  Hiroshi Matsushita ,  Norihiko Tsuchiya ,  Katsuya Okumura

发明人： Tsunetoshi Arikado ,  Masao Iwase ,  Soichi Nadahara ,  Yuso Udo ,  Yukihiro Ushiku ,  Shinichi Nitta ,  Moriya Miyashita ,  Junji Sugamoto ,  Hiroaki Yamada ,  Hajime Nagano ,  Katsujiro Tanzawa ,  Hiroshi Matsushita ,  Norihiko Tsuchiya ,  Katsuya Okumura

IPC分类号： H01L29/06

CPC分类号： H01L23/544 ,  H01L2223/54406 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y10S438/974 ,  H01L2924/00

摘要： A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.

公开(公告)号：US20060076624A1

公开(公告)日：2006-04-13

申请号：US11282784

申请日：2005-11-18

申请人： Hajime Nagano ,  Kiyotaka Miyano ,  Ichiro Mizushima

发明人： Hajime Nagano ,  Kiyotaka Miyano ,  Ichiro Mizushima

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/76251 ,  H01L21/84

摘要： A semiconductor substrate is disclosed which comprises a first single crystal silicon layer, an insulator formed to partially cover one main surface of the first single crystal silicon layer, a second single crystal silicon layer formed to cover a region of the first single crystal silicon layer which is not covered with the insulator, and to cover an edge portion of the insulator adjacent to the region, and a non-single crystal silicon layer formed on the insulator, the interface between the non-single crystal silicon layer and the second single crystal silicon layer being positioned on the insulator.

摘要翻译： 公开了一种半导体衬底，其包括第一单晶硅层，形成为部分地覆盖第一单晶硅层的一个主表面的绝缘体，形成为覆盖第一单晶硅层的区域的第二单晶硅层， 不覆盖绝缘体，并且覆盖邻近该区域的绝缘体的边缘部分，以及形成在绝缘体上的非单晶硅层，非单晶硅层与第二单晶硅之间的界面 层位于绝缘体上。

公开(公告)号：US06906384B2

公开(公告)日：2005-06-14

申请号：US10096655

申请日：2002-03-14

申请人： Takashi Yamada ,  Tsutomu Sato ,  Shinichi Nitta ,  Hajime Nagano ,  Ichiro Mizushima ,  Hisato Oyamatsu ,  Yoshihiro Minami ,  Shinji Miyano ,  Osamu Fujii

发明人： Takashi Yamada ,  Tsutomu Sato ,  Shinichi Nitta ,  Hajime Nagano ,  Ichiro Mizushima ,  Hisato Oyamatsu ,  Yoshihiro Minami ,  Shinji Miyano ,  Osamu Fujii

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/10 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L27/10861 ,  H01L21/76243 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/78639

摘要： A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

摘要翻译： 半导体器件包括第一和第二半导体层以及第一和第二MOS晶体管。 第一半导体层设置在半导体衬底上并与之电连接。 第二半导体层设置在第一半导体层附近，并且经由绝缘膜和空腔中的一个形成在半导体基板的上方。 第一和第二MOS晶体管分别设置在第一和第二半导体层上，并且各自具有平行于第一和第二半导体层之间的边界排列的栅电极。

公开(公告)号：US08532615B2

公开(公告)日：2013-09-10

申请号：US12395445

申请日：2009-02-27

申请人： Hajime Nagano

发明人： Hajime Nagano

IPC分类号： H04M1/66

CPC分类号： H04W60/04 ,  G08B25/008 ,  H04W84/045

摘要： To provide a security technique (a base station and a mobile terminal) for easily guarding a building such as a house for an average family or a small office at a low price by using a cellular phone terminal and a small base station (femtocell). A base station (FCL) of a mobile communication system placed in a building includes a communication unit (140) for communicating with the mobile communication system via a communication line; an obtaining unit (123) for obtaining an opened state of a fitting set to an opening of the building from the fitting or a switch placed near the fitting for detecting the opened state of the fitting; a registering unit (121) for registering information on a mobile terminal that uses the base station; a processing unit (122) for processing location registration of the mobile terminal; and a control unit (120) for controlling the communication unit to transmit a predetermined message to a predetermined addressee via the communication line if information received from the mobile terminal does not match the information registered in the registering unit when the location registration of the mobile terminal is performed by the processing unit after the opened state of the fitting is obtained.

摘要翻译： 为了提供一种安全技术（基站和移动终端），通过使用蜂窝电话终端和小型基站（femtocell），以便于以较低的价格容易地保护一般家庭或小型办公室的建筑物。 放置在建筑物中的移动通信系统的基站（FCL）包括通信单元（140），用于经由通信线路与移动通信系统进行通信; 获取单元（123），用于从配件或设置在配件附近的开关中获得对建筑物的开口设置的配件的打开状态，以检测配件的打开状态; 注册单元，用于在使用该基站的移动终端上注册信息; 处理单元（122），用于处理移动终端的位置登记; 以及控制单元（120），用于当移动终端的位置登记时，控制通信单元经由通信线路将预定消息发送到预定的收件人，如果从移动终端接收到的信息与注册单元中登记的信息不匹配 在获得配件的打开状态之后由处理单元执行。

公开(公告)号：US07884415B2

公开(公告)日：2011-02-08

申请号：US12405457

申请日：2009-03-17

申请人： Hajime Nagano

发明人： Hajime Nagano

IPC分类号： H01L29/788 ,  H01L29/76 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/11524 ,  H01L21/28273 ,  H01L21/764 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825

摘要： In a semiconductor device, each of a plurality of floating gate electrodes has an upper end, a lower end and an intermediate portion between the upper and lower ends and is formed so that the intermediate portion has a smaller length in a gate-length direction than each of the upper and lower ends. Each of a plurality of control gate electrodes has an upper end, a lower end and an intermediate portion between the upper and lower ends and is formed so that the intermediate portion has a smaller length in a gate-length direction than each of the upper and lower ends. Each of a plurality of inter-electrode insulating films includes a first air gap formed in a first portion corresponding to the intermediate portion of each floating gate electrode and a second air gap formed in a second portion corresponding to the intermediate portion of each control gate electrode.

摘要翻译： 在半导体器件中，多个浮栅电极中的每一个具有上端和下端以及位于上端和下端之间的中间部分，并且形成为使得中间部分的栅极长度方向上的长度小于 每个上下端。 多个控制栅电极中的每一个具有上端，下端和位于上端和下端之间的中间部分，并且形成为使得中间部分在栅极长度方向上的长度小于上部和下部中的每一个 下端 多个电极间绝缘膜中的每一个包括形成在与每个浮栅电极的中间部分对应的第一部分中的第一气隙和形成在与每个控制栅电极的中间部分对应的第二部分中的第二气隙 。

公开(公告)号：US07525154B2

公开(公告)日：2009-04-28

申请号：US10852511

申请日：2004-05-25

申请人： Hajime Nagano ,  Ichiro Mizushima ,  Kiyotaka Miyano

发明人： Hajime Nagano ,  Ichiro Mizushima ,  Kiyotaka Miyano

IPC分类号： H01L29/72

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78687

摘要： A semiconductor substrate and a manufacturing method therefore, and a semiconductor device using the semiconductor substrate comprise a strained Si region and unstrained Si region formed at substantially the same level. In an aspect of the invention, a semiconductor substrate is provided by comprising a support substrate, a first semiconductor region including a first silicon layer formed above the support substrate, a second semiconductor region including a strained second silicon layer formed above the support substrate, a surface of the second silicon layer being formed at substantially the same level as a surface of the first silicon layer, and an insulating film at an interface between the first semiconductor region and the second semiconductor region.

摘要翻译： 因此，半导体衬底及其制造方法以及使用该半导体衬底的半导体器件包括形成在大致相同电平的应变Si区域和未应变Si区域。 在本发明的一个方面中，提供一种半导体衬底，其包括支撑衬底，包括形成在支撑衬底上方的第一硅层的第一半导体区域，包括形成在支撑衬底上方的应变第二硅层的第二半导体区域， 所述第二硅层的表面形成在与所述第一硅层的表面基本相同的水平面上，以及在所述第一半导体区域和所述第二半导体区域之间的界面处形成绝缘膜。

公开(公告)号：US07439112B2

公开(公告)日：2008-10-21

申请号：US11498774

申请日：2006-08-04

申请人： Hajime Nagano ,  Shinichi Nitta ,  Hisato Oyamatsu

发明人： Hajime Nagano ,  Shinichi Nitta ,  Hisato Oyamatsu

IPC分类号： H01L21/8242 ,  H01L21/84

CPC分类号： H01L27/10894 ,  H01L21/76251 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76278 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing method includes selectively removing portions of a buried oxide layer and first semiconductor layer in an SOI substrate having the first semiconductor layer formed above a semiconductor substrate with the buried oxide layer disposed therebetween and exposing part of the semiconductor substrate, removing an exposed region of the semiconductor substrate in a depth direction, and burying a second semiconductor region in the region from which part of the semiconductor substrate has been removed in the depth direction.

摘要翻译： 一种半导体器件制造方法，包括：选择性地去除SOI衬底中的一部分掩埋氧化物层和第一半导体层，所述SOI衬底具有形成于半导体衬底上方的所述掩埋氧化物层的第一半导体层，并且暴露所述半导体衬底的一部分， 区域，并且在半导体衬底的一部分已经在深度方向上被去除的区域中埋入第二半导体区域。

公开(公告)号：US07420249B2

公开(公告)日：2008-09-02

申请号：US11849682

申请日：2007-09-04

申请人： Tsutomu Sato ,  Hajime Nagano ,  Ichiro Mizushima ,  Takashi Yamada ,  Yuso Udo ,  Shinichi Nitta

发明人： Tsutomu Sato ,  Hajime Nagano ,  Ichiro Mizushima ,  Takashi Yamada ,  Yuso Udo ,  Shinichi Nitta

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L21/764 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/10897 ,  H01L27/1203 ,  H01L27/1207

摘要： A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insulating film and a cavity, and a third semiconductor layer surrounding the second semiconductor layer, the third semiconductor layer being formed on the semiconductor substrate.

摘要翻译： 一种半导体器件，包括形成在半导体衬底上的第一半导体层，围绕第一半导体层的第二半导体层，在半导体衬底上形成有绝缘膜和空腔中的一个的第二半导体层和围绕 所述第二半导体层，所述第三半导体层形成在所述半导体衬底上。

公开(公告)号：US07187035B2

公开(公告)日：2007-03-06

申请号：US10237206

申请日：2002-09-09

申请人： Hajime Nagano ,  Takashi Yamada ,  Tsutomu Sato ,  Ichiro Mizushima ,  Hisato Oyamatsu

发明人： Hajime Nagano ,  Takashi Yamada ,  Tsutomu Sato ,  Ichiro Mizushima ,  Hisato Oyamatsu

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A method of manufacturing a semiconductor device substrate is disclosed, which comprises forming a mask layer patterned on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the insulating layer, etching a protective layer deposited thinner on the semiconductor substrate than the thickness of the insulating layer to form a sidewall protective film which covers a side surface of the trench, etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and growing a single-crystalline layer from the surface of the semiconductor substrate exposed as a result of etching the insulating layer.

摘要翻译： 公开了一种制造半导体器件衬底的方法，其包括通过电绝缘层形成在半导体层与半导体衬底的表面绝缘的图案化的掩模层，根据掩模层的图案蚀刻半导体层以形成 导通绝缘层的沟槽，蚀刻比半导体衬底更薄的保护层比绝缘层的厚度形成覆盖沟槽侧表面的侧壁保护膜，从绝缘层的底表面蚀刻绝缘层 沟槽到半导体衬底; 以及从蚀刻绝缘层而暴露的半导体衬底的表面生长单晶层。

公开(公告)号：US07148543B2

公开(公告)日：2006-12-12

申请号：US10828337

申请日：2004-04-21

申请人： Takashi Yamada ,  Hajime Nagano ,  Ichiro Mizushima ,  Tsutomu Sato ,  Hisato Oyamatsu ,  Shinichi Nitta

发明人： Takashi Yamada ,  Hajime Nagano ,  Ichiro Mizushima ,  Tsutomu Sato ,  Hisato Oyamatsu ,  Shinichi Nitta

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L29/00 ,  H01L29/04 ,  H01L29/06

CPC分类号： H01L27/10894 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10861 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

摘要翻译： 半导体芯片包括基底基板，在基底基板的一部分上具有体积生长层的体器件区域，在基底基板上具有埋入绝缘体的SOI器件区域和埋入绝缘体上的硅层，以及边界层 位于体器件区域和SOI器件区域之间的边界处。 本体装置区域具有第一装置制造表面，其中大块装置位于本体生长层上。 SOI器件区域具有第二器件制造表面，其中SOI器件位于硅层上。 第一和第二装置制造表面被定位在基本均匀的水平。