公开(公告)号：US20130148429A1

公开(公告)日：2013-06-13

申请号：US13705143

申请日：2012-12-04

申请人： Chan-Kyung Kim ,  Yun-Sang Lee ,  Chul-Woo Park ,  Hong-Sun Hwang

发明人： Chan-Kyung Kim ,  Yun-Sang Lee ,  Chul-Woo Park ,  Hong-Sun Hwang

IPC分类号： G11C7/06 ,  G11C11/16 ,  G11C16/26 ,  G11C13/00

CPC分类号： G11C7/06 ,  G11C7/065 ,  G11C7/222 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/4091 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/26 ,  G11C16/28 ,  G11C27/02 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2213/71 ,  H01L27/222 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06

摘要： Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.

摘要翻译： 提供了一种存储器件，其具有被配置为接收第一CSL信号以输入或输出数据的第一开关。 第二开关被配置为接收第二CSL信号。 感测和锁存电路（SLC）耦合在第一和第二开关之间。 并且至少一个存储器单元耦合到第二开关。 第二开关被配置为响应于第二CSL信号来控制至少一个存储器单元的读取或写入操作的定时，例如，可以在不超过约5ns的范围内执行读取操作。 SLC作为写入模式的锁存器和读取模式下的放大器工作。 存储器装置可以包括存储器系统的一部分或包括这种存储器装置或系统的其他装置。 还提供了使用这种存储器件执行读和写操作的方法。

公开(公告)号：US08873324B2

公开(公告)日：2014-10-28

申请号：US13240049

申请日：2011-09-22

申请人： Chul-Woo Park ,  Joo-Sun Choi ,  Hong-Sun Hwang

发明人： Chul-Woo Park ,  Joo-Sun Choi ,  Hong-Sun Hwang

IPC分类号： G11C7/00

CPC分类号： G11C11/40618 ,  G11C11/40622 ,  G11C11/408

摘要： A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging.

摘要翻译： 生成具有刷新周期的刷新地址，以刷新刷新的存储器件。 当刷新地址是第二地址而不是具有第二地址的第一强单元时，对具有第一地址的弱小区执行相应的刷新。 当刷新地址是第三地址时，在具有第三地址的第一强单元或第二强单元之一上执行相应的刷新。 仅对第一，第二和第三地址中的一个存储地址信息，从而可以减少存储容量。 在替代方面，当刷新地址是至少一个预定地址中的任一个以导致刷新利用时，依赖于标志，在弱小区，第一强小区或第二强小区中的一个上执行相应的刷新。

公开(公告)号：US20120300568A1

公开(公告)日：2012-11-29

申请号：US13240049

申请日：2011-09-22

申请人： Chul-Woo Park ,  Joo-Sun Choi ,  Hong-Sun Hwang

发明人： Chul-Woo Park ,  Joo-Sun Choi ,  Hong-Sun Hwang

IPC分类号： G11C11/402

CPC分类号： G11C11/40618 ,  G11C11/40622 ,  G11C11/408

摘要： A refresh address is generated with a refresh period for refreshing a memory device with refresh leveraging. A respective refresh is performed on a weak cell having a first address when the refresh address is a second address instead of on a first strong cell having the second address. A respective refresh is performed on one of the first strong cell or a second strong cell having a third address when the refresh address is the third address. Address information is stored for only one of the first, second, and third addresses such that memory capacity may be reduced. In alternative aspects, a respective refresh is performed on one of a weak cell, a first strong cell, or a second strong cell depending on a flag when the refresh address is any of at least one predetermined address to result in refresh leveraging.

摘要翻译： 生成具有刷新周期的刷新地址，以刷新刷新的存储器件。 当刷新地址是第二地址而不是具有第二地址的第一强单元时，对具有第一地址的弱小区执行相应的刷新。 当刷新地址是第三地址时，在具有第三地址的第一强单元或第二强单元之一上执行相应的刷新。 仅对第一，第二和第三地址中的一个存储地址信息，从而可以减少存储容量。 在替代方面，当刷新地址是至少一个预定地址中的任一个以导致刷新利用时，依赖于标志，在弱小区，第一强小区或第二强小区中的一个上执行相应的刷新。

公开(公告)号：US09171589B2

公开(公告)日：2015-10-27

申请号：US13705143

申请日：2012-12-04

申请人： Chan-Kyung Kim ,  Yun-Sang Lee ,  Chul-Woo Park ,  Hong-Sun Hwang

发明人： Chan-Kyung Kim ,  Yun-Sang Lee ,  Chul-Woo Park ,  Hong-Sun Hwang

IPC分类号： G11C16/04 ,  G11C7/06 ,  G11C13/00 ,  G11C11/16 ,  G11C16/26

CPC分类号： G11C7/06 ,  G11C7/065 ,  G11C7/222 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/4091 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/26 ,  G11C16/28 ,  G11C27/02 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2213/71 ,  H01L27/222 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06

摘要： Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.

摘要翻译： 提供了一种存储器件，其具有被配置为接收第一CSL信号以输入或输出数据的第一开关。 第二开关被配置为接收第二CSL信号。 感测和锁存电路（SLC）耦合在第一和第二开关之间。 并且至少一个存储器单元耦合到第二开关。 第二开关被配置为响应于第二CSL信号来控制至少一个存储器单元的读取或写入操作的定时，例如，可以在不超过约5ns的范围内执行读取操作。 SLC作为写入模式的锁存器和读取模式下的放大器工作。 存储器装置可以包括存储器系统的一部分或包括这种存储器装置或系统的其他装置。 还提供了使用这种存储器件执行读和写操作的方法。

公开(公告)号：US08654595B2

公开(公告)日：2014-02-18

申请号：US13604688

申请日：2012-09-06

申请人： Chan-Kyung Kim ,  Hong-Sun Hwang ,  Chul-Woo Park ,  Sang-Beom Kang ,  Hyung-Rok Oh

发明人： Chan-Kyung Kim ,  Hong-Sun Hwang ,  Chul-Woo Park ,  Sang-Beom Kang ,  Hyung-Rok Oh

IPC分类号： G11C7/02

CPC分类号： G11C5/145 ,  G11C7/12 ,  G11C11/1673

摘要： A nonvolatile memory device comprises a nonvolatile cell array comprising a memory cell and a reference cell, a clamping circuit electrically connected to the memory cell and configured to clamp a voltage applied to a data sensing line during a read operation, and a clamping voltage generation unit configured to generate a clamping voltage responsive to a first voltage having a level based on the reference cell, and to feed back the clamping voltage to the clamping circuit.

摘要翻译： 非易失性存储器件包括非易失性单元阵列，其包括存储单元和参考单元，钳位电路电连接到存储单元并且被配置为在读取操作期间钳位施加到数据感测线的电压，以及钳位电压产生单元 被配置为响应于具有基于参考单元的电平的第一电压产生钳位电压，并且将钳位电压反馈到钳位电路。

公开(公告)号：US08441852B2

公开(公告)日：2013-05-14

申请号：US13024566

申请日：2011-02-10

申请人： Chul-Woo Park ,  Hong-Sun Hwang ,  In-Gyu Baek ,  Dong-Hyun Sohn

发明人： Chul-Woo Park ,  Hong-Sun Hwang ,  In-Gyu Baek ,  Dong-Hyun Sohn

IPC分类号： G11C11/34

CPC分类号： H01L21/77 ,  G11C5/025 ,  G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/24

摘要： A stacked semiconductor memory device comprises a semiconductor substrate having a functional circuit, a plurality of memory cell array layers, and at least one connection layer. The memory cell array layers are stacked above the semiconductor substrate. The connection layers are stacked above the semiconductor substrate independent of the memory cell array layers. The connection layers electrically connect memory cell selecting lines arranged on the memory cell array layers to the functional circuit.

摘要翻译： 叠层半导体存储器件包括具有功能电路，多个存储单元阵列层以及至少一个连接层的半导体衬底。 存储单元阵列层堆叠在半导体衬底之上。 连接层堆叠在半导体衬底之上，独立于存储单元阵列层。 连接层将布置在存储单元阵列层上的存储单元选择线电连接到功能电路。

公开(公告)号：US09978430B2

公开(公告)日：2018-05-22

申请号：US13733884

申请日：2013-01-03

申请人： Eun-Sung Seo ,  Chul-Woo Park ,  Hong-Sun Hwang

发明人： Eun-Sung Seo ,  Chul-Woo Park ,  Hong-Sun Hwang

IPC分类号： G11C7/00 ,  G11C11/406

CPC分类号： G11C7/00 ,  G11C11/40611

摘要： A memory system includes at least one memory device and a memory controller. The at least one memory device includes a refresh request circuit that generates refresh request signals at timings based on data retention times of memory cells, such as based on individual data retention times of a memory cell row. The memory controller schedules operation commands for the at least one memory device in response to the received refresh request signals.

公开(公告)号：US09070465B2

公开(公告)日：2015-06-30

申请号：US13586973

申请日：2012-08-16

申请人： Jong-Pil Son ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hyun-Ho Choi

发明人： Jong-Pil Son ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hyun-Ho Choi

IPC分类号： G11C11/00 ,  G11C11/16

CPC分类号： G11C11/161 ,  G11C11/1659 ,  G11C11/1673

摘要： An anti-fuse circuit includes an array of anti-fuses. Each anti-fuse has a tunneling magneto-resistance (TMR) element series connected with a transistor, such that breakdown of a magnetic tunnel junction (MTJ) in response to an applied first voltage stores fuse information. A sensing circuit senses and amplifies respective output signals provided by the anti-fuses.

摘要翻译： 反熔丝电路包括一组抗熔丝。 每个反熔丝具有与晶体管连接的隧道磁阻（TMR）元件串联，使得响应于施加的第一电压的磁隧道结（MTJ）的击穿存储熔丝信息。 感测电路感测并放大由防熔丝提供的各自的输出信号。

公开(公告)号：US08780656B2

公开(公告)日：2014-07-15

申请号：US13015847

申请日：2011-01-28

申请人： Chul-Woo Park ,  Hong-Sun Hwang ,  Sang-Beom Kang ,  Won-Seok Lee

发明人： Chul-Woo Park ,  Hong-Sun Hwang ,  Sang-Beom Kang ,  Won-Seok Lee

IPC分类号： G11C7/00 ,  G11C5/02

CPC分类号： G11C5/025 ,  G11C29/80

摘要： A stacked semiconductor memory device comprises memory cell array layers that are stacked in an inverted wedge shape and have different redundancy sizes from each other. The stacked semiconductor memory device has space for vertical connection between layers, a relatively small size, and a relatively high yield.

摘要翻译： 层叠的半导体存储器件包括以倒置的楔形堆叠并且具有彼此不同的冗余尺寸的存储单元阵列层。 层叠的半导体存储器件具有用于层之间的垂直连接的空间，相对较小的尺寸和相对较高的产量。

公开(公告)号：US07382668B2

公开(公告)日：2008-06-03

申请号：US11319247

申请日：2005-12-27

申请人： Ki-Won Park ,  Hong-Sun Hwang ,  Sung-Ryul Kim

发明人： Ki-Won Park ,  Hong-Sun Hwang ,  Sung-Ryul Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/1204

摘要： A full-stress testable memory device having an open bit line architecture and a method of testing the memory device. The memory device of the invention includes dummy bit lines, and a voltage controller connected to the dummy bit lines. The voltage controller alternately provides a first variable control voltage and a second variable control voltage to the dummy bit lines during a test mode. In accordance with a method of testing the memory device, a fixed voltage is provided to the dummy bit lines of the edge sub-arrays during a normal operation mode. However, during a test mode, the fixed voltage being applied to the dummy bit line is replaced with a supply voltage and/or a ground voltage, so that all of the sub-arrays can be equally tested.

摘要翻译： 具有开放位线架构的全压力可测试存储器件和测试存储器件的方法。 本发明的存储器件包括虚拟位线和连接到虚拟位线的电压控制器。 电压控制器在测试模式期间交替地向虚拟位线提供第一可变控制电压和第二可变控制电压。 根据测试存储器件的方法，在正常操作模式期间，将固定电压提供给边缘子阵列的虚拟位线。 然而，在测试模式期间，施加到虚拟位线的固定电压被替换为电源电压和/或接地电压，使得可以对所有子阵列进行同样的测试。