摘要:
Control circuitry used with the combination of a control switch (typically a gated diode switch GDS) which is coupled to a control (gate) terminal of a like load switch which consists essentially of first and second p-n-p transistors. The collector of the first p-n-p transistor is coupled to an anode of the control switch. The emitter of the first p-n-p transistor is coupled to the base of the second p-n-p transistor and to a control circuitry input terminal. The collector of the second p-n-p transistor is coupled to a gate terminal of the control switch. The control circuitry limits undesirable current flow into the load switch and has fewer components than commonly used control circuitry which performs a like function.
摘要:
Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.
摘要:
Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.
摘要:
Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.
摘要:
Electronic modules and methods of fabrication are provided implementing a first metallization level directly on a chips-first chip layer. The chips-first layer includes chips, each with a pad mask over an upper surface and openings to expose chip contact pads. Structural dielectric material surrounds and physically contacts the side surfaces of the chips, and has an upper surface which is parallel to an upper surface of the chips. A metallization layer is disposed over the front surface of the chips-first layer, residing at least partially on the pad masks of the chips, and extending over one or more edges of the chips. Together, the pad masks of the chips, and the structural dielectric material electrically isolate the metallization layer from the edges of the chips, and from one or more electrical structures of the chips in the chips-first layer.
摘要:
An integrated circuit in which a large potential can be maintained between the source of the device and the substrate on which this device and other devices are fabricated is described. The circuit employs a minority carrier sink region to remove minority carriers from the gate region of a MOS depletion device. The sink region is shielded from the substrate by a buried layer which prevents punch-through between the sink region and the substrate.
摘要:
A circuit for driving an output between two voltage states in response to a control signal is disclosed. The circuit requires a very small amount of power in its quiescent state. The circuit comprises a first switch including first and second control terminals that provides a conductive path from a first source of potential to an output terminal when the potential difference between the control terminals is less than a first predetermined threshold value and for electrically isolating the first source of potential from the output terminal when the potential difference between the control terminals is greater than the first predetermined threshold value, and a second switch that provides a conductive path between a second source of potential and the output terminal when the first switch electrically isolates the first source of potential from the output terminal. The second switch electrically isolates the output terminal from the second source of potential when the first switch provides a conductive path from the first source of potential to the output terminal. The circuit also includes a control circuit for causing the potential difference between the first and second control terminals of the first switch to be greater than the first threshold value in response to a predetermined signal on the circuit input terminal and causes the potential difference between the first and second control terminals of the first switch to be less than the first threshold value when the predetermined signal is not present on the circuit input terminal.
摘要:
A switch is provided wherein a piezoelectric bimorph element is used to provide many separately controllable, closely spaced switchable contacts. The element includes at least two oppositely extending fingers connected by a common spine. The element spine is mounted to a case with the fingers spaced from an inner case surface. Electronic circuit means are mounted on the element spine for applying a separate electrical potential to each of the element fingers. A separate movable electrical contact is disposed on each of the element fingers spaced from the spine and insulated from the means for applying the separate electrical potentials to the fingers. A separate stationary contact is provided on an inner case surface opposite each of the movable contacts. In operations, a separate electrical potential is applied to each of the element fingers for selectively causing each finger to deflect and force its movable contact into electrical connection with the opposing stationary contact.
摘要:
A method of bonding two structures together with an adhesive line of controlled thickness is provided. The method includes: applying an adhesive of controlled thickness to a first surface of a first structure; at least partially curing the adhesive; applying additional adhesive to the partially cured adhesive applied to the first surface or to a second surface of a second structure; holding the first structure and the second structure in alignment with the first surface and the second surface disposed in spaced, opposing relation; applying a force to the first structure and/or the second structure to squeeze the additional adhesive between the second surface and the partially cured adhesive applied to the first surface to reduce a thickness of the additional adhesive; and at least partially curing the additional adhesive to bond the first and second structures together.
摘要:
Methods of fabricating a base layer circuit structure are provided. One fabrication method includes: providing an alignment carrier having a support surface; forming a plurality of electrically conductive structures above the support surface of the alignment carrier; disposing a structural material around and physically contacting the side surfaces of the electrically conductive structures formed above the support surface, the structural material having an upper surface coplanar with or parallel to the upper surface of one or more of the electrically conductive structures; exposing, if covered, the upper surfaces of the electrically conductive structures to facilitate electrical connection to the structures; and separating the alignment carrier from the base layer circuit structure. The base layer circuit structure includes the plurality of electrically conductive structures and the structural material surrounding and physically contacting the electrically conductive structures.