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公开(公告)号：US4697118A
公开(公告)日：1987-09-29
申请号：US896792
申请日：1986-08-15
CPC分类号： H01H57/00 , H01L41/094
摘要： A switch is provided wherein a piezoelectric bimorph element is used to provide many separately controllable, closely spaced switchable contacts. The element includes at least two oppositely extending fingers connected by a common spine. The element spine is mounted to a case with the fingers spaced from an inner case surface. Electronic circuit means are mounted on the element spine for applying a separate electrical potential to each of the element fingers. A separate movable electrical contact is disposed on each of the element fingers spaced from the spine and insulated from the means for applying the separate electrical potentials to the fingers. A separate stationary contact is provided on an inner case surface opposite each of the movable contacts. In operation, a separate electrical potential is applied to each of the element fingers for selectively causing each finger to deflect and force its movable contact into electrical connection with the opposing stationary contact.
摘要翻译： 提供了一种开关，其中使用压电双晶片元件来提供许多可分离的可紧密间隔的可切换触点。 该元件包括由普通脊柱连接的至少两个相对延伸的指状物。 元件脊柱安装在手指与内壳表面间隔开的外壳上。 电子电路装置安装在元件脊上，以将单独的电位施加到每个元件指状物。 单独的可移动电触头设置在与脊柱间隔开的每个元件指状物上，并与用于将分离的电势施加到手指的装置绝缘。 在与每个可移动触头相对的内壳表面上设置单独的固定触点。 在操作中，单独的电势被施加到每个元件指状件，用于选择性地使每个指状物偏转并迫使其可动触点与相对的固定触点电连接。
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公开(公告)号：US4742263A
公开(公告)日：1988-05-03
申请号：US88827
申请日：1987-08-24
CPC分类号： H01H57/00 , H01L41/094
摘要： A switch is provided wherein a piezoelectric bimorph element is used to provide many separately controllable, closely spaced switchable contacts. The element includes at least two oppositely extending fingers connected by a common spine. The element spine is mounted to a case with the fingers spaced from an inner case surface. Electronic circuit means are mounted on the element spine for applying a separate electrical potential to each of the element fingers. A separate movable electrical contact is disposed on each of the element fingers spaced from the spine and insulated from the means for applying the separate electrical potentials to the fingers. A separate stationary contact is provided on an inner case surface opposite each of the movable contacts. In operations, a separate electrical potential is applied to each of the element fingers for selectively causing each finger to deflect and force its movable contact into electrical connection with the opposing stationary contact.
摘要翻译： 提供了一种开关，其中使用压电双晶片元件来提供许多可分离的可紧密间隔的可切换触点。 该元件包括由普通脊柱连接的至少两个相对延伸的指状物。 元件脊柱安装在手指与内壳表面间隔开的外壳上。 电子电路装置安装在元件脊上，以将单独的电位施加到每个元件指状物。 单独的可移动电触点设置在与脊柱间隔开的每个元件指状件上，并与用于将单独的电势施加到手指的装置绝缘。 在与每个可移动触头相对的内壳表面上设置单独的固定触点。 在操作中，单独的电位被施加到每个元件指状件，用于选择性地使每个指状物偏转并且将其可动触点强制成与相对的固定触点电连接。
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公开(公告)号：US4868620A
公开(公告)日：1989-09-19
申请号：US219288
申请日：1988-07-14
CPC分类号： H01L29/7302 , H01L29/7835 , H01L29/7838
摘要： An integrated circuit in which a large potential can be maintained between the source of the device and the substrate on which this device and other devices are fabricated is described. The circuit employs a minority carrier sink region to remove minority carriers from the gate region of a MOS depletion device. The sink region is shielded from the substrate by a buried layer which prevents punch-through between the sink region and the substrate.
摘要翻译： 描述了其中可以在器件的源极与其上制造该器件和其它器件的衬底之间保持大电位的集成电路。 该电路采用少数载流子阱区以从MOS耗尽装置的栅极区域去除少数载流子。 通过掩埋层将宿区域与衬底隔离，防止了宿区域和衬底之间的穿透。
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4.发明授权公开(公告)号：US08384199B2
公开(公告)日：2013-02-26
申请号：US12144720
申请日：2008-06-24
IPC分类号： H01L23/552
CPC分类号： H05K3/30 , H01L21/568 , H01L21/6835 , H01L23/29 , H01L23/3128 , H01L23/5389 , H01L23/552 , H01L24/19 , H01L24/82 , H01L24/96 , H01L25/0652 , H01L2221/68345 , H01L2223/6677 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16 , H01L2224/16227 , H01L2224/16235 , H01L2224/20 , H01L2224/211 , H01L2224/24137 , H01L2224/2518 , H01L2224/96 , H01L2225/1035 , H01L2225/1058 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/3511 , H05K1/0206 , H05K1/0218 , H05K1/185 , H05K3/4644 , H05K2201/09563 , H05K2201/096 , H05K2201/10371 , H05K2201/10674 , H05K2203/0733 , Y10T29/49121 , Y10T29/49124 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49155 , H01L2924/00
摘要： Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.
摘要翻译： 提供了电路结构和制造方法，以便于以紧凑的封装实现完整的电子系统。 在一个实施例中，电路结构包括具有延伸穿过其中的导电结构的芯片 - 第一多芯片基底层。 互连层设置在多芯层的前表面上，并且包括电连接到芯片的接触焊盘和延伸穿过结构材料的导电结构的互连金属化。 设置在多芯层的后表面上的再分配层包括还电连接到延伸穿过结构材料的导电结构的再分布金属化。 输入/输出触点排列在再分配层上，包括在多芯层内的至少一些集成电路芯片的下表面上，并且通过再分布金属化，导电结构和互连金属化电连接到集成电路的接触焊盘 多芯片层的芯片。
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5.发明授权Integrated structures and fabrication methods thereof implementing a cell phone or other electronic system 有权实现蜂窝电话或其他电子系统的集成结构及其制造方法公开(公告)号：US07619901B2
公开(公告)日：2009-11-17
申请号：US12144715
申请日：2008-06-24
IPC分类号： H05K1/18
CPC分类号： H05K3/30 , H01L21/568 , H01L21/6835 , H01L23/29 , H01L23/3128 , H01L23/5389 , H01L23/552 , H01L24/19 , H01L24/82 , H01L24/96 , H01L25/0652 , H01L2221/68345 , H01L2223/6677 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16 , H01L2224/16227 , H01L2224/16235 , H01L2224/20 , H01L2224/211 , H01L2224/24137 , H01L2224/2518 , H01L2224/96 , H01L2225/1035 , H01L2225/1058 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/3511 , H05K1/0206 , H05K1/0218 , H05K1/185 , H05K3/4644 , H05K2201/09563 , H05K2201/096 , H05K2201/10371 , H05K2201/10674 , H05K2203/0733 , Y10T29/49121 , Y10T29/49124 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49155 , H01L2924/00
摘要： Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.
摘要翻译： 提供了电路结构和制造方法，以便于以紧凑的封装实现完整的电子系统。 在一个实施例中，电路结构包括具有延伸穿过其中的导电结构的芯片 - 第一多芯片基底层。 互连层设置在多芯层的前表面上，并且包括电连接到芯片的接触焊盘和延伸穿过结构材料的导电结构的互连金属化。 设置在多芯层的后表面上的再分配层包括还电连接到延伸穿过结构材料的导电结构的再分布金属化。 输入/输出触点排列在再分配层上，包括在多芯层内的至少一些集成电路芯片的下表面上，并且通过再分布金属化，导电结构和互连金属化电连接到集成电路的接触焊盘 多芯片层的芯片。
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公开(公告)号：US06555908B1
公开(公告)日：2003-04-29
申请号：US09501177
申请日：2000-02-10
IPC分类号： H01L2334
CPC分类号： H01L23/3114 , H01L21/56 , H01L23/49811 , H01L23/5389 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/05147 , H01L2224/05155 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/12105 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/16225 , H01L2224/16235 , H01L2224/20 , H01L2224/211 , H01L2224/24137 , H01L2224/32225 , H01L2224/73267 , H01L2224/94 , H01L2224/97 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/30107 , H01L2924/351 , H05K3/4007 , H01L2224/82 , H01L2224/83 , H01L2224/11 , H01L2924/00 , H01L2924/00014
摘要： Structures and methods are provided for electrically interconnecting and absorbing stress between a first electrical structure and a second electrical structure. In one embodiment, non-conductive compliant bumps are disposed on at least one of the structures and a metal layer is provided over a surface of the non-conductive compliant bumps. The metal layer facilitates electrical coupling of the metal on the surfaces of the compliant bumps with multiple contact pads of the structure supporting the bumps. The non-conductive compliant bumps can be fabricated of a low modulus material which has a high ultimate elongation property (LMHE dielectric). The LMHE dielectric can have a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least twenty percent. In an alternate embodiment, at least one mushroom-shaped conductive bump is disposed above a compliant dielectric layer on one of the first electrical structure or the second electrical structure. The mushroom-shaped conductive bumps are employed to electrically interconnect the first and second electrical structures. The compliant dielectric layer can be a LMHE dielectric.
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公开(公告)号：US06396148B1
公开(公告)日：2002-05-28
申请号：US09501200
申请日：2000-02-10
IPC分类号： H01L2348
CPC分类号： H01L24/12 , H01L21/288 , H01L21/568 , H01L21/6835 , H01L23/3114 , H01L23/3128 , H01L23/522 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/04105 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05647 , H01L2224/13022 , H01L2224/13099 , H01L2224/20 , H01L2224/211 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/15311 , H01L2924/00014
摘要： Chips first packaging structures and methods of fabrication are presented which employ electroless metallizations. An electroless barrier metal is disposed over and in electrical contact with at least one aluminum contact pad of the chips first integrated circuit. The electroless barrier metal is a first electroless metal and is a different material than the at least one aluminum contact pad. An electroless interconnect metal is disposed above and electrically contacts the electroless barrier metal. The electroless interconnect metal is a second electroless metal, which is different from the first electroless metal. As an example, the electroless barrier metal comprises electroless nickel and the electroless interconnect metal comprises electroless copper.
摘要翻译： 提出了采用无电金属化的芯片第一包装结构和制造方法。 无电阻挡金属设置在芯片第一集成电路的至少一个铝接触焊盘上并与之电接触。 无电阻挡金属是第一无电金属，并且是与至少一个铝接触垫不同的材料。 无电互连金属设置在无电屏障金属的上方并与之电接触。 无电互连金属是与第一无电金属不同的第二无电金属。 作为示例，无电阻挡金属包括无电镀镍，无电互连金属包括无电解铜。
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8.发明授权Method of processing siloxane-polyimides for electronic packaging applications 失效用于电子封装应用的硅氧烷 - 聚酰亚胺加工方法
公开(公告)号：US4897153A
公开(公告)日：1990-01-30
申请号：US342153
申请日：1989-04-24
申请人： Herbert S. Cole , James E. Kohl
发明人： Herbert S. Cole , James E. Kohl
IPC分类号： H05K3/26 , B32B27/00 , B32B27/16 , H01L21/312 , H01L21/48 , H01L21/768 , H01L23/12 , H01L23/538 , H05K3/00 , H05K3/38 , H05K3/46
CPC分类号： H01L21/481 , H01L21/3121 , H01L21/76801 , H01L21/76814 , H01L21/76826 , H01L21/76835 , H01L23/5389 , H01L2924/0002 , H05K3/0017 , H05K3/381 , H05K3/4644
摘要： A method of forming a multilayer metallization pattern using siloxane polyimide dielectric layers comprises forming the first siloxane polyimide layer, laser etching holes in the first layer, plasma etching the first layer to be sure the holes are clean, then cleaning the surface of the first layer in an etchant for silicon oxide, after which the metallization layer is formed and patterned and a second siloxane polyimide layer is formed thereover with good adhesion.
摘要翻译： 使用硅氧烷聚酰亚胺电介质层形成多层金属化图案的方法包括形成第一硅氧烷聚酰亚胺层，第一层中的激光蚀刻孔，等离子体蚀刻第一层以确保孔清洁，然后清洁第一层的表面 在氧化硅的蚀刻剂中，之后形成并图案化金属化层，并在其上形成第二硅氧烷聚酰亚胺层，具有良好的粘附性。
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公开(公告)号：US4860334A
公开(公告)日：1989-08-22
申请号：US248405
申请日：1988-09-23
申请人： James E. Kohl , Donald L. Watrous
发明人： James E. Kohl , Donald L. Watrous
CPC分类号： H04Q3/0012 , H04Q1/24
摘要： A method and apparatus for detecting and locating defective crosspoint switches in a path consisting of a plurality of conducting segments connected by switch points is disclosed. The method and apparatus utilize the change in capacitance of the path which occurs when the switches are operated in a predetermined order.
摘要翻译： 公开了一种用于检测和定位由切换点连接的多个导电段组成的路径中的有缺陷的交叉点开关的方法和设备。 该方法和装置利用当开关以预定顺序操作时发生的路径的电容变化。
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公开(公告)号：US08590145B2
公开(公告)日：2013-11-26
申请号：US12580537
申请日：2009-10-16
IPC分类号： H05K3/30
CPC分类号： H05K3/30 , H01L21/568 , H01L21/6835 , H01L23/29 , H01L23/3128 , H01L23/5389 , H01L23/552 , H01L24/19 , H01L24/82 , H01L24/96 , H01L25/0652 , H01L2221/68345 , H01L2223/6677 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16 , H01L2224/16227 , H01L2224/16235 , H01L2224/20 , H01L2224/211 , H01L2224/24137 , H01L2224/2518 , H01L2224/96 , H01L2225/1035 , H01L2225/1058 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H01L2924/3511 , H05K1/0206 , H05K1/0218 , H05K1/185 , H05K3/4644 , H05K2201/09563 , H05K2201/096 , H05K2201/10371 , H05K2201/10674 , H05K2203/0733 , Y10T29/49121 , Y10T29/49124 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49155 , H01L2924/00
摘要： Methods of fabricating a circuit structure are provided. The fabrication method includes: forming a chip layer, which includes obtaining at least one chip and disposing a structural material around and physically contacting the side surface(s) of each chip in the chip layer. The structural material has an upper surface substantially coplanar with or parallel to an upper surface of each chip and defines at least a portion of a front surface of the chip layer, and has a lower surface substantially coplanar with or parallel to a lower surface of each chip, which defines at least portion of a back surface of the chip layer. The method further includes forming at least one strengthening structure over the back surface of the chip layer. The strengthening structure is formed to strengthen an interface between the chip(s) and the structural material.
摘要翻译： 提供制造电路结构的方法。 制造方法包括：形成芯片层，其包括获得至少一个芯片并且在芯片层中的每个芯片的侧表面周围设置结构材料并物理接触芯片层。 结构材料具有与每个芯片的上表面基本上共面或平行的上表面，并且限定了芯片层的前表面的至少一部分，并且具有与每个芯片的下表面基本上共面或平行于下表面的下表面 芯片，其限定了芯片层的背表面的至少一部分。 该方法还包括在芯片层的背面上形成至少一个强化结构。 形成强化结构以加强芯片和结构材料之间的界面。
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