公开(公告)号：US08384199B2

公开(公告)日：2013-02-26

申请号：US12144720

申请日：2008-06-24

申请人： Charles W. Eichelberger ,  James E. Kohl

发明人： Charles W. Eichelberger ,  James E. Kohl

IPC分类号： H01L23/552

CPC分类号： H05K3/30 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0218 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0733 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

摘要： Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.

摘要翻译： 提供了电路结构和制造方法，以便于以紧凑的封装实现完整的电子系统。 在一个实施例中，电路结构包括具有延伸穿过其中的导电结构的芯片 - 第一多芯片基底层。 互连层设置在多芯层的前表面上，并且包括电连接到芯片的接触焊盘和延伸穿过结构材料的导电结构的互连金属化。 设置在多芯层的后表面上的再分配层包括还电连接到延伸穿过结构材料的导电结构的再分布金属化。 输入/输出触点排列在再分配层上，包括在多芯层内的至少一些集成电路芯片的下表面上，并且通过再分布金属化，导电结构和互连金属化电连接到集成电路的接触焊盘 多芯片层的芯片。

公开(公告)号：US07619901B2

公开(公告)日：2009-11-17

申请号：US12144715

申请日：2008-06-24

申请人： Charles W. Eichelberger ,  James E. Kohl

发明人： Charles W. Eichelberger ,  James E. Kohl

IPC分类号： H05K1/18

CPC分类号： H05K3/30 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0218 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0733 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

摘要： Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.

摘要翻译： 提供了电路结构和制造方法，以便于以紧凑的封装实现完整的电子系统。 在一个实施例中，电路结构包括具有延伸穿过其中的导电结构的芯片 - 第一多芯片基底层。 互连层设置在多芯层的前表面上，并且包括电连接到芯片的接触焊盘和延伸穿过结构材料的导电结构的互连金属化。 设置在多芯层的后表面上的再分配层包括还电连接到延伸穿过结构材料的导电结构的再分布金属化。 输入/输出触点排列在再分配层上，包括在多芯层内的至少一些集成电路芯片的下表面上，并且通过再分布金属化，导电结构和互连金属化电连接到集成电路的接触焊盘 多芯片层的芯片。

公开(公告)号：US06555908B1

公开(公告)日：2003-04-29

申请号：US09501177

申请日：2000-02-10

申请人： Charles W. Eichelberger ,  James E. Kohl

发明人： Charles W. Eichelberger ,  James E. Kohl

IPC分类号： H01L2334

CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K3/4007 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/00014

摘要： Structures and methods are provided for electrically interconnecting and absorbing stress between a first electrical structure and a second electrical structure. In one embodiment, non-conductive compliant bumps are disposed on at least one of the structures and a metal layer is provided over a surface of the non-conductive compliant bumps. The metal layer facilitates electrical coupling of the metal on the surfaces of the compliant bumps with multiple contact pads of the structure supporting the bumps. The non-conductive compliant bumps can be fabricated of a low modulus material which has a high ultimate elongation property (LMHE dielectric). The LMHE dielectric can have a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least twenty percent. In an alternate embodiment, at least one mushroom-shaped conductive bump is disposed above a compliant dielectric layer on one of the first electrical structure or the second electrical structure. The mushroom-shaped conductive bumps are employed to electrically interconnect the first and second electrical structures. The compliant dielectric layer can be a LMHE dielectric.

公开(公告)号：US06396148B1

公开(公告)日：2002-05-28

申请号：US09501200

申请日：2000-02-10

申请人： Charles W. Eichelberger ,  James E. Kohl ,  Michael E. Rickley

发明人： Charles W. Eichelberger ,  James E. Kohl ,  Michael E. Rickley

IPC分类号： H01L2348

CPC分类号： H01L24/12 ,  H01L21/288 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/522 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014

摘要： Chips first packaging structures and methods of fabrication are presented which employ electroless metallizations. An electroless barrier metal is disposed over and in electrical contact with at least one aluminum contact pad of the chips first integrated circuit. The electroless barrier metal is a first electroless metal and is a different material than the at least one aluminum contact pad. An electroless interconnect metal is disposed above and electrically contacts the electroless barrier metal. The electroless interconnect metal is a second electroless metal, which is different from the first electroless metal. As an example, the electroless barrier metal comprises electroless nickel and the electroless interconnect metal comprises electroless copper.

摘要翻译： 提出了采用无电金属化的芯片第一包装结构和制造方法。 无电阻挡金属设置在芯片第一集成电路的至少一个铝接触焊盘上并与之电接触。 无电阻挡金属是第一无电金属，并且是与至少一个铝接触垫不同的材料。 无电互连金属设置在无电屏障金属的上方并与之电接触。 无电互连金属是与第一无电金属不同的第二无电金属。 作为示例，无电阻挡金属包括无电镀镍，无电互连金属包括无电解铜。

公开(公告)号：US08590145B2

公开(公告)日：2013-11-26

申请号：US12580537

申请日：2009-10-16

申请人： Charles W. Eichelberger ,  James E. Kohl

发明人： Charles W. Eichelberger ,  James E. Kohl

IPC分类号： H05K3/30

CPC分类号： H05K3/30 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0218 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0733 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

摘要： Methods of fabricating a circuit structure are provided. The fabrication method includes: forming a chip layer, which includes obtaining at least one chip and disposing a structural material around and physically contacting the side surface(s) of each chip in the chip layer. The structural material has an upper surface substantially coplanar with or parallel to an upper surface of each chip and defines at least a portion of a front surface of the chip layer, and has a lower surface substantially coplanar with or parallel to a lower surface of each chip, which defines at least portion of a back surface of the chip layer. The method further includes forming at least one strengthening structure over the back surface of the chip layer. The strengthening structure is formed to strengthen an interface between the chip(s) and the structural material.

摘要翻译： 提供制造电路结构的方法。 制造方法包括：形成芯片层，其包括获得至少一个芯片并且在芯片层中的每个芯片的侧表面周围设置结构材料并物理接触芯片层。 结构材料具有与每个芯片的上表面基本上共面或平行的上表面，并且限定了芯片层的前表面的至少一部分，并且具有与每个芯片的下表面基本上共面或平行于下表面的下表面 芯片，其限定了芯片层的背表面的至少一部分。 该方法还包括在芯片层的背面上形成至少一个强化结构。 形成强化结构以加强芯片和结构材料之间的界面。

公开(公告)号：US08169065B2

公开(公告)日：2012-05-01

申请号：US12644380

申请日：2009-12-22

申请人： James E. Kohl ,  Charles W. Eichelberger

发明人： James E. Kohl ,  Charles W. Eichelberger

IPC分类号： H01L23/48 ,  H01L21/30

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/20 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/221 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Stackable circuit structures and methods of fabrication are provided employing first level metallization directly on a chips-first layer(s), which includes: a chip(s), each with a pad mask over its upper surface and openings exposing its contact pads; electrically conductive structures; and structural dielectric material surrounding the side surfaces of the chips and the conductive structures. Each chips-first layer further includes a metallization layer on the front surface of the layer, residing at least partially on the pad mask and extending over an edge of the chip. Together, the pad mask and the structural material electrically isolate the metallization layer from the chip. Input/output interconnect structures physically and electrically contact the metallization layer over the front surface and/or the lower surfaces of the electrically conductive structures at the back surface of the chips-first layer, to facilitate input/output connection to chips of the layers in a stack.

摘要翻译： 提供了可堆叠的电路结构和制造方法，其在芯片第一层上直接采用第一级金属化，其包括：芯片，每个芯片在其上表面上具有焊盘掩模，并且露出其接触焊盘; 导电结构; 以及围绕芯片和导电结构的侧表面的结构介电材料。 每个芯片第一层还包括在该层的前表面上的金属化层，其至少部分地驻留在焊盘掩模上并在芯片的边缘上延伸。 一起，焊盘掩模和结构材料将金属化层与芯片电隔离。 输入/输出互连结构在芯片第一层的后表面处物理地和电接触导电结构的前表面和/或下表面上的金属化层，以便于输入/输出与层的芯片的连接 一堆

公开(公告)号：US07863090B2

公开(公告)日：2011-01-04

申请号：US12144725

申请日：2008-06-24

申请人： Charles W. Eichelberger ,  James E. Kohl

发明人： Charles W. Eichelberger ,  James E. Kohl

IPC分类号： H01L21/48 ,  H01L23/02

CPC分类号： H05K3/30 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0218 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0733 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

摘要： Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.

摘要翻译： 提供了电路结构和制造方法，以便于以紧凑的封装实现完整的电子系统。 在一个实施例中，电路结构包括具有延伸穿过其中的导电结构的芯片 - 第一多芯片基底层。 互连层设置在多芯层的前表面上，并且包括电连接到芯片的接触焊盘和延伸穿过结构材料的导电结构的互连金属化。 设置在多芯层的后表面上的再分配层包括还电连接到延伸穿过结构材料的导电结构的再分布金属化。 输入/输出触点排列在再分配层上，包括在多芯层内的至少一些集成电路芯片的下表面上，并且通过再分布金属化，导电结构和互连金属化电连接到集成电路的接触焊盘 多芯片层的芯片。

公开(公告)号：US06426545B1

公开(公告)日：2002-07-30

申请号：US09502078

申请日：2000-02-10

申请人： Charles W. Eichelberger ,  James E. Kohl

发明人： Charles W. Eichelberger ,  James E. Kohl

IPC分类号： H01L2308

CPC分类号： H01L24/19 ,  H01L23/3157 ,  H01L23/49894 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/82 ,  H01L2224/83

摘要： Structures and methods are provided for absorbing stress between a first electrical structure and a second electrical structure connected together, wherein the first and second structures have different coefficients of thermal expansion. A dielectric material is disposed on at least one of the first and second electrical structures. This dielectric material is a low modulus material which has a high ultimate elongation property (LMHE dielectric). Preferably, the LMHE dielectric has a Young's modulus of less than 50,000 psi and an ultimate elongation property of at least 20 percent. The LMHE dielectric can be photo patternable to facilitate formation of via openings therein and a metal layer is formed above the LMHE dielectric which has conductors capable of expanding or contracting with the dielectric. Conductors of the metal layer disposed above the dielectric and connected to vias in the dielectric have a length significantly greater than the maximum displacement due to thermal expansion between the first and second electrical structures, e.g., a length which is at least five times the displacement.

摘要翻译： 提供了用于吸收连接在一起的第一电气结构和第二电气结构之间的应力的结构和方法，其中第一和第二结构具有不同的热膨胀系数。 电介质材料设置在第一和第二电结构中的至少一个上。 该介电材料是具有高极限伸长率（LMHE电介质）的低模量材料。 优选地，LMHE电介质的杨氏模量小于50,000psi，极限伸长率至少为20％。 LMHE电介质可以是光可图案化的，以便于其中形成通孔开口，并且在LMHE电介质上形成金属层，其具有能够与电介质膨胀或收缩的导体。 设置在电介质上方并连接到电介质中的通孔的金属层的导体的长度显着大于由于第一和第二电结构之间的热膨胀而引起的最大位移，例如至少为位移的五倍的长度。

公开(公告)号：US08564119B2

公开(公告)日：2013-10-22

申请号：US12611405

申请日：2009-11-03

申请人： Charles W. Eichelberger ,  James E. Kohl

发明人： Charles W. Eichelberger ,  James E. Kohl

IPC分类号： H01L23/36

CPC分类号： H05K3/30 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0218 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0733 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

摘要： Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.

摘要翻译： 提供了电路结构和制造方法，以便于以紧凑的封装实现完整的电子系统。 在一个实施例中，电路结构包括具有延伸穿过其中的导电结构的芯片 - 第一多芯片基底层。 互连层设置在多芯层的前表面上，并且包括电连接到芯片的接触焊盘和延伸穿过结构材料的导电结构的互连金属化。 设置在多芯层的后表面上的再分配层包括还电连接到延伸穿过结构材料的导电结构的再分布金属化。 输入/输出触点排列在再分配层上，包括在多芯层内的至少一些集成电路芯片的下表面上，并且通过再分布金属化，导电结构和互连金属化电连接到集成电路的接触焊盘 多芯片层的芯片。

公开(公告)号：US08324020B2

公开(公告)日：2012-12-04

申请号：US12611412

申请日：2009-11-03

申请人： Charles W. Eichelberger ,  James E. Kohl

发明人： Charles W. Eichelberger ,  James E. Kohl

IPC分类号： H01L21/00

CPC分类号： H05K3/30 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0218 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0733 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

摘要： Circuit structures and methods of fabrication are provided for facilitating implementing a complete electronic system in a compact package. The circuit structure includes, in one embodiment, a chips-first multichip base layer with conductive structures extending therethrough. An interconnect layer is disposed over the front surface of the multichip layer and includes interconnect metallization electrically connected to contact pads of the chips and to conductive structures extending through the structural material. A redistribution layer, disposed over the back surface of the multichip layer, includes a redistribution metallization also electrically connected to conductive structures extending through the structural material. Input/output contacts are arrayed over the redistribution layer, including over the lower surfaces of at least some integrated circuit chips within the multichip layer, and are electrically connected through the redistribution metallization, conductive structures, and interconnect metallization to contact pads of the integrated circuit chips of the multichip layer.

摘要翻译： 提供了电路结构和制造方法，以便于以紧凑的封装实现完整的电子系统。 在一个实施例中，电路结构包括具有延伸穿过其中的导电结构的芯片 - 第一多芯片基底层。 互连层设置在多芯层的前表面上，并且包括电连接到芯片的接触焊盘和延伸穿过结构材料的导电结构的互连金属化。 设置在多芯层的后表面上的再分配层包括还电连接到延伸穿过结构材料的导电结构的再分布金属化。 输入/输出触点排列在再分配层上，包括在多芯层内的至少一些集成电路芯片的下表面上，并且通过再分布金属化，导电结构和互连金属化电连接到集成电路的接触焊盘 多芯片层的芯片。