公开(公告)号：US5434439A

公开(公告)日：1995-07-18

申请号：US163647

申请日：1993-12-09

申请人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

发明人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10817 ,  H01L27/10852

摘要： The DRAM according to the present invention comprises so-called cylindrical stacked type capacitors. Each of the cylindrical stacked type capacitors comprises a base portion extending flat on an insulation layer and a surface of a substrate, and a cylindrical portion extending vertically and upwardly from the base portion. Then, the cylindrical portion vertically and upwardly protrudes from an outermost peripheral position of the base portion. As a result, an area where electrodes of the capacitor and capacitance of the capacitor can be increased. Furthermore, with a bit line located below an electrode layer of the capacitor, adjacent capacitors above the bit line can be isolated. Accordingly, it is possible to prevent the bit line contact from defining an isolation distance between the capacitors. Furthermore, an isolating layer patterned by etching is used as an isolating region between the capacitors and a lower electrode of the capacitor is formed along a surface of the isolating layer to form an isolation region between the adjacent capacitors. In addition, the lower electrode of the cylindrical stacked type capacitor is integrally formed by using a step formed in the insulation layer. As a result, the manufacturing step is simplified.

公开(公告)号：US5523596A

公开(公告)日：1996-06-04

申请号：US403614

申请日：1995-03-14

申请人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika

发明人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika

IPC分类号： H01L27/04 ,  H01L21/318 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  Y10S438/954

摘要： A capacitor includes a polycrystalline silicon layer 1 as a lower electrode layer, a dielectric layer 112, and a polycrystalline silicon layer 113 as an upper electrode layer. The dielectric layer 112 is formed by an oxynitride film 2, a silicon nitride film 3 and a top oxide film 4. A film thickness t.sub.3 of the top oxide film 4 is controlled to be less than 20 .ANG.. Capacitance of the capacitor can be increased while improving the duration of life of the dielectric layer, resulting in a highly reliable capacitor.

摘要翻译： 电容器包括作为下电极层的多晶硅层1，电介质层112和作为上电极层的多晶硅层113。 电介质层112由氧氮化物膜2，氮化硅膜3和顶部氧化物膜4形成。顶部氧化膜4的膜厚度t3被控制为小于20安培。 可以增加电容器的电容，同时改善电介质层的寿命，导致高度可靠的电容器。

公开(公告)号：US5683929A

公开(公告)日：1997-11-04

申请号：US467641

申请日：1995-06-06

申请人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika

发明人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika

IPC分类号： H01L27/04 ,  H01L21/318 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  Y10S438/954

摘要： A capacitor includes a polycrystalline silicon layer 1 as a lower electrode layer, a dielectric layer 112, and a polycrystalline silicon layer 113 as an upper electrode layer. The dielectric layer 112 is formed by an oxynitride film 2, a silicon nitride film 3 and a top oxide film 4. A film thickness t.sub.3 of the top oxide film 4 is controlled to be less than 20 .ANG.. Capacitance of the capacitor can be increased while improving the duration of life of the dielectric layer, resulting in a highly reliable capacitor.

摘要翻译： 电容器包括作为下电极层的多晶硅层1，电介质层112和作为上电极层的多晶硅层113。 电介质层112由氧氮化物膜2，氮化硅膜3和顶部氧化物膜4形成。顶部氧化膜4的膜厚度t3被控制为小于20安培。 可以增加电容器的电容，同时改善电介质层的寿命，导致高度可靠的电容器。

公开(公告)号：US5173752A

公开(公告)日：1992-12-22

申请号：US690824

申请日：1991-04-26

申请人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

发明人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/108 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L27/10873 ,  H01L23/485 ,  H01L27/10817 ,  H01L2924/0002 ,  Y10S257/90

摘要： A semiconductor device incloudes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

摘要翻译： 半导体器件包括MOS型场效应晶体管，其栅电极（4）的表面被第一绝缘膜（5）覆盖，左侧和右侧设置有一对第二绝缘膜（10）。 第一导电层（12,13）形成在源/漏区（8,11）的表面上，并且一对第二绝缘膜（10）中的一个位于栅电极的一侧的表面 （4）。 至少在没有形成第一导电层（12,13）的第二绝缘膜（10）的表面上形成第三绝缘膜（24b）。 在第三绝缘膜（24b）的表面和形成有第三绝缘膜（24b）的源/漏区（8,11）上设置第二导电层（18）。 该结构能够提供可以独立于图案化抗蚀剂掩模的步骤中的误差的影响的自对准中形成接触孔的半导体器件。

公开(公告)号：US5141891A

公开(公告)日：1992-08-25

申请号：US777498

申请日：1991-10-17

申请人： Hideaki Arima ,  Natsuo Ajika

发明人： Hideaki Arima ,  Natsuo Ajika

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/66606 ,  H01L21/28525 ,  H01L29/0847 ,  H01L29/7836

摘要： An MIS-type semiconductor device comprises PSD structure and LDD structure. The LDD structure comprises high concentration impurity regions formed by thermally diffusing impurities which have been contained in source/drain electrode conductive layers made of polysilicon onto a semiconductor substrate, and low concentration impurity regions formed through ion implantation using resist patterned on channel regions and the source/drain electrode conductive layers as mask. A gate electrode is formed, after formation of the low concentration impurity regions, to cover them and have its edges overlap the source/drain electrode conductive layers. The LDD structure suppresses the short channel effects which might be caused in the MIS-type semiconductor device and thus enables channels length to be miniaturized while the PSD structure enables also miniaturization of source/drain structure.

摘要翻译： MIS型半导体器件包括PSD结构和LDD结构。 LDD结构包括通过将包含在由多晶硅制成的源极/漏极导电层中的杂质热粘合到半导体衬底上而形成的高浓度杂质区域，以及通过使用在沟道区域上图案化的抗蚀剂通过离子注入形成的低浓度杂质区域 /漏电极导电层作为掩模。 在形成低浓度杂质区之后，形成栅电极以覆盖它们并且其边缘与源/漏电极导电层重叠。 LDD结构抑制了可能在MIS型半导体器件中引起的短沟道效应，并且因此使得沟道长度能够小型化，同时PSD结构也能够使源极/漏极结构的小型化。

公开(公告)号：US4989054A

公开(公告)日：1991-01-29

申请号：US339546

申请日：1989-04-17

申请人： Hideaki Arima ,  Natsuo Ajika

发明人： Hideaki Arima ,  Natsuo Ajika

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L29/7883

摘要： First, second, third and fourth impurity regions are formed on a major surface of a semiconductor substrate with prescribed spaces, to define first, second and third channel regions in portions held between the same. A select gate is formed on the first channel region through an insulating film, to define a transistor with the first and second impurity regions. A part of a control gate is formed on the third channel region through an insulating film, to define a transistor with the third and fourth impurity regions. A floating gate is formed on the second channel region and parts of the select gate and the control gate through an insulating film, to define a transistor with the second and third impurity regions. Both end portions of the floating gate are inwardly separated from upper positions of respective outer ends of parts of the select gate and the control gate, in order to improve an effect of shielding the floating gate against a fourth impurity region. Another part of the control gate is formed on the floating gate through an insulating film. The first impurity region is connected to a bit line and the fourth impurity region is connected to a source region respectively.

摘要翻译： 在具有预定间隔的半导体衬底的主表面上形成第一，第二，第三和第四杂质区域，以限定保持在其中的部分中的第一，第二和第三沟道区域。 通过绝缘膜在第一沟道区上形成选择栅，以限定具有第一和第二杂质区的晶体管。 控制栅极的一部分通过绝缘膜形成在第三沟道区上，以限定具有第三和第四杂质区的晶体管。 通过绝缘膜在第二沟道区域和选择栅极和控制栅极的部分上形成浮栅，以限定具有第二和第三杂质区的晶体管。 浮动栅极的两个端部与选择栅极和控制栅极的部分的相应外端的上部位置向内分离，以便改善屏蔽浮置栅极抵抗第四杂质区域的效果。 控制栅极的另一部分通过绝缘膜在浮栅上形成。 第一杂质区域连接到位线，第四杂质区域分别与源极区域连接。

公开(公告)号：US5898606A

公开(公告)日：1999-04-27

申请号：US841372

申请日：1997-04-30

申请人： Shinichi Kobayashi ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Takeshi Nakayama ,  Tomoshi Futatsuya ,  Natsuo Ajika ,  Yuichi Kunori ,  Hiroshi Onoda ,  Atsushi Fukumoto ,  Makoto Ohi

发明人： Shinichi Kobayashi ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Takeshi Nakayama ,  Tomoshi Futatsuya ,  Natsuo Ajika ,  Yuichi Kunori ,  Hiroshi Onoda ,  Atsushi Fukumoto ,  Makoto Ohi

IPC分类号： G11C16/04 ,  G11C16/16 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  G11C7/00

CPC分类号： H01L27/11517 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/16 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546 ,  H01L29/7883

摘要： In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

摘要翻译： 在擦除时，电子同时从多个存储单元的源中注入到浮动栅极中。 因此，多个存储单元的阈值电压增加。 在编程中，电子从所选择的存储单元的浮动栅极发射到漏极。 因此，所选存储单元的阈值电压降低。

公开(公告)号：US5338957A

公开(公告)日：1994-08-16

申请号：US110151

申请日：1993-08-23

申请人： Atsushi Fukumoto ,  Makoto Ohi ,  Hiroshi Onoda ,  Natsuo Ajika ,  Yuichi Kunori

发明人： Atsushi Fukumoto ,  Makoto Ohi ,  Hiroshi Onoda ,  Natsuo Ajika ,  Yuichi Kunori

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/68 ,  G11C11/34

CPC分类号： H01L27/115

摘要： The width of a charge storage electrode and a control electrode in the column direction is set to be wider above an element isolation region than that above a channel region. Therefore, the capacitance between the control electrode and the charge storage electrode can be increased to improve the coupling ratio in a nonvolatile semiconductor memory device. Also, a first interconnection layer is equal in height above the control electrode and above the channel region, so that patterning of the first interconnection layer can be carried out easily and precisely.

摘要翻译： 在列方向上的电荷存储电极和控制电极的宽度被设定为比元件隔离区域高于沟道区域以上的宽度。 因此，可以增加控制电极和电荷存储电极之间的电容，以提高非易失性半导体存储器件中的耦合比。 此外，第一互连层在控制电极上方高于沟道区域的高度相等，使得可以容易且精确地执行第一互连层的图案化。

公开(公告)号：US4988635A

公开(公告)日：1991-01-29

申请号：US356144

申请日：1989-05-24

申请人： Natsuo Ajika ,  Hideaki Arima

发明人： Natsuo Ajika ,  Hideaki Arima

IPC分类号： H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A memory cell of 1 bit is constituted by 1 selecting transistor and 1 memory transistor in an EEPROM. One of the source-drain regions is commonly used by the selecting transistor and the memory transistor. The commonly used source-drain region is manufactured through the following steps. First, a gate electrode of the transistor is formed. An oxide film is deposited on the entire surface. A resist is applied thereon and is etched back to expose a surface of the oxide film on the gate electrode. Thereafter, the oxide films deposited on the side surfaces of the gate electrode are removed to form opening portions. Impurities are implanted to the silicon substrate utilizing the opening portions.

摘要翻译： 1位的存储单元由EEPROM中的1个选择晶体管和1个存储晶体管构成。 源极 - 漏极区之一通常由选择晶体管和存储晶体管使用。 常用的源极 - 漏极区域通过以下步骤制造。 首先，形成晶体管的栅电极。 氧化膜沉积在整个表面上。 将抗蚀剂施加在其上并被回蚀以暴露栅电极上的氧化膜的表面。 此后，去除沉积在栅电极的侧表面上的氧化膜以形成开口部分。 利用开口部分将杂质植入硅衬底。

公开(公告)号：US5240872A

公开(公告)日：1993-08-31

申请号：US925148

申请日：1992-08-06

申请人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

发明人： Kaoru Motonami ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yoshinori Okumura ,  Yasushi Matsui

IPC分类号： H01L21/8242 ,  H01L23/485 ,  H01L27/108

CPC分类号： H01L27/10873 ,  H01L23/485 ,  H01L27/10817 ,  H01L2924/0002

摘要： A semiconductor device includes a MOS type field effect transistor whose gate electrode (4) has its surface covered with a first insulating film (5) and left and right sides provided with a pair of second insulating films (10). A first conductive layer (12, 13) is formed on the surface of the source/drain region (8, 11) and the surface of one of a pair of second insulating films (10) which are positioned on one side of the gate electrode (4). A third insulating film (24b) is formed at least on the surface of the second insulating film (10) on which the first conductive layer (12, 13) is not formed. A second conductive layer (18) is provided on the surface of the third insulating film (24b) and on the source/drain region (8, 11) on which the third insulating film (24b) is formed. This structure enables provision of a semiconductor device in which a contact hole can be formed in self-alignment, independent from the influence of errors in the step of patterning a resist mask.

摘要翻译： 半导体器件包括MOS型场效应晶体管，其栅极（4）的表面被第一绝缘膜（5）覆盖，左右侧设置有一对第二绝缘膜（10）。 第一导电层（12,13）形成在源/漏区（8,11）的表面上，并且一对第二绝缘膜（10）中的一个位于栅电极的一侧的表面 （4）。 至少在没有形成第一导电层（12,13）的第二绝缘膜（10）的表面上形成第三绝缘膜（24b）。 在第三绝缘膜（24b）的表面和形成有第三绝缘膜（24b）的源/漏区（8,11）上设置第二导电层（18）。 该结构能够提供可以独立于图案化抗蚀剂掩模的步骤中的误差的影响的自对准中形成接触孔的半导体器件。