公开(公告)号：US5381365A

公开(公告)日：1995-01-10

申请号：US91675

申请日：1993-06-30

申请人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

发明人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

IPC分类号： H01L27/108 ,  H01L29/68 ,  H01L27/10

CPC分类号： H01L27/10817

摘要： The DRAM according to the present invention comprises so-called cylindrical stacked type capacitors. Each of the cylindrical stacked type capacitors comprises a base portion extending flat on an insulation layer and a surface of a substrate, and a cylindrical portion extending vertically and upwardly from the base portion. Then, the cylindrical portion vertically and upwardly protrudes from an outermost peripheral position of the base portion. As a result, an area where electrodes of the capacitor and capacitance of the capacitor can be increased. Furthermore, with a bit line located below an electrode layer of the capacitor, adjacent capacitors above the bit line can be isolated. Accordingly, it is possible to prevent the bit line contact from defining an isolation distance between the capacitors. Furthermore, an isolating layer patterned by etching is used as an isolating region between the capacitors and a lower electrode of the capacitor is formed along a surface of the isolating layer to form an isolation region between the adjacent capacitors. In addition, the lower electrode of the cylindrical stacked type capacitor is integrally formed by using a step formed in the insulation layer. As a result, the manufacturing step is simplified.

摘要翻译： 根据本发明的DRAM包括所谓的圆柱形堆叠型电容器。 每个圆柱形堆叠型电容器包括在绝缘层和基板的表面上平坦延伸的基部，以及从基部垂直和向上延伸的圆柱形部分。 然后，圆筒部从基部的最外周位置向上方突出。 结果，可以增加电容器的电极和电容器的电容的区域。 此外，通过位于电容器的电极层下方的位线，可以隔离位线上方的相邻电容器。 因此，可以防止位线接触限定电容器之间的隔离距离。 此外，通过蚀刻图案化的隔离层用作电容器之间的隔离区域，并且电容器的下电极沿着隔离层的表面形成，以在相邻的电容器之间形成隔离区域。 此外，圆柱形堆叠型电容器的下电极通过使用形成在绝缘层中的台阶整体地形成。 结果，简化了制造步骤。

公开(公告)号：US5141891A

公开(公告)日：1992-08-25

申请号：US777498

申请日：1991-10-17

申请人： Hideaki Arima ,  Natsuo Ajika

发明人： Hideaki Arima ,  Natsuo Ajika

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L29/66606 ,  H01L21/28525 ,  H01L29/0847 ,  H01L29/7836

摘要： An MIS-type semiconductor device comprises PSD structure and LDD structure. The LDD structure comprises high concentration impurity regions formed by thermally diffusing impurities which have been contained in source/drain electrode conductive layers made of polysilicon onto a semiconductor substrate, and low concentration impurity regions formed through ion implantation using resist patterned on channel regions and the source/drain electrode conductive layers as mask. A gate electrode is formed, after formation of the low concentration impurity regions, to cover them and have its edges overlap the source/drain electrode conductive layers. The LDD structure suppresses the short channel effects which might be caused in the MIS-type semiconductor device and thus enables channels length to be miniaturized while the PSD structure enables also miniaturization of source/drain structure.

摘要翻译： MIS型半导体器件包括PSD结构和LDD结构。 LDD结构包括通过将包含在由多晶硅制成的源极/漏极导电层中的杂质热粘合到半导体衬底上而形成的高浓度杂质区域，以及通过使用在沟道区域上图案化的抗蚀剂通过离子注入形成的低浓度杂质区域 /漏电极导电层作为掩模。 在形成低浓度杂质区之后，形成栅电极以覆盖它们并且其边缘与源/漏电极导电层重叠。 LDD结构抑制了可能在MIS型半导体器件中引起的短沟道效应，并且因此使得沟道长度能够小型化，同时PSD结构也能够使源极/漏极结构的小型化。

公开(公告)号：US4989054A

公开(公告)日：1991-01-29

申请号：US339546

申请日：1989-04-17

申请人： Hideaki Arima ,  Natsuo Ajika

发明人： Hideaki Arima ,  Natsuo Ajika

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L29/7883

摘要： First, second, third and fourth impurity regions are formed on a major surface of a semiconductor substrate with prescribed spaces, to define first, second and third channel regions in portions held between the same. A select gate is formed on the first channel region through an insulating film, to define a transistor with the first and second impurity regions. A part of a control gate is formed on the third channel region through an insulating film, to define a transistor with the third and fourth impurity regions. A floating gate is formed on the second channel region and parts of the select gate and the control gate through an insulating film, to define a transistor with the second and third impurity regions. Both end portions of the floating gate are inwardly separated from upper positions of respective outer ends of parts of the select gate and the control gate, in order to improve an effect of shielding the floating gate against a fourth impurity region. Another part of the control gate is formed on the floating gate through an insulating film. The first impurity region is connected to a bit line and the fourth impurity region is connected to a source region respectively.

摘要翻译： 在具有预定间隔的半导体衬底的主表面上形成第一，第二，第三和第四杂质区域，以限定保持在其中的部分中的第一，第二和第三沟道区域。 通过绝缘膜在第一沟道区上形成选择栅，以限定具有第一和第二杂质区的晶体管。 控制栅极的一部分通过绝缘膜形成在第三沟道区上，以限定具有第三和第四杂质区的晶体管。 通过绝缘膜在第二沟道区域和选择栅极和控制栅极的部分上形成浮栅，以限定具有第二和第三杂质区的晶体管。 浮动栅极的两个端部与选择栅极和控制栅极的部分的相应外端的上部位置向内分离，以便改善屏蔽浮置栅极抵抗第四杂质区域的效果。 控制栅极的另一部分通过绝缘膜在浮栅上形成。 第一杂质区域连接到位线，第四杂质区域分别与源极区域连接。

公开(公告)号：US5672533A

公开(公告)日：1997-09-30

申请号：US555414

申请日：1995-11-09

申请人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L21/8242 ,  H01L29/68 ,  H01L29/76 ,  H01L29/78 ,  H01L29/92 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L27/1085 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/66659

摘要： Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.

摘要翻译： 公开了一种半导体存储器件，其中可以有效地减少电容器和源极/漏极区域之间的结区中的晶体缺陷和晶体管的短沟道效应。 半导体存储器件包括在电容器连接的栅电极侧，形成为具有比位线侧的侧壁宽度大的侧壁以及源极/漏极区， 电容器被连接并且被形成为具有比相对的源极/漏极区的扩散深度更大的扩散深度。 因此，源极/漏极区域有效地防止在电容器和连接到电容器的源极/漏极区域之间的结区域中产生晶体缺陷，并且侧壁有效地降低了短沟道效应。

公开(公告)号：US5597755A

公开(公告)日：1997-01-28

申请号：US457193

申请日：1995-06-01

申请人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

发明人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10817 ,  H01L27/10852

摘要： A method of manufacturing a semiconductor memory device having stacked capacitors is disclosed. After forming a capacitor isolating layer on an insulation layer and forming a contact hole in the insulation layer, a first conductive layer is formed on the insulating layer and the capacitor isolating layer and on an inner surface of the contact hole. The first conductive layer is partially etched and removed by using an etch-back technique to be isolated into a first capacitor portion and a second capacitor portion. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer.

摘要翻译： 公开了一种制造具有层叠电容器的半导体存储器件的方法。 在绝缘层上形成电容器隔离层并在绝缘层中形成接触孔之后，在绝缘层和电容器隔离层上以及接触孔的内表面上形成第一导电层。 通过使用蚀刻技术将第一导电层部分地蚀刻和去除，以将其隔离成第一电容器部分和第二电容器部分。 在第一导电层上形成电介质层。 在介电层上形成第二导电层。

公开(公告)号：US4988635A

公开(公告)日：1991-01-29

申请号：US356144

申请日：1989-05-24

申请人： Natsuo Ajika ,  Hideaki Arima

发明人： Natsuo Ajika ,  Hideaki Arima

IPC分类号： H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A memory cell of 1 bit is constituted by 1 selecting transistor and 1 memory transistor in an EEPROM. One of the source-drain regions is commonly used by the selecting transistor and the memory transistor. The commonly used source-drain region is manufactured through the following steps. First, a gate electrode of the transistor is formed. An oxide film is deposited on the entire surface. A resist is applied thereon and is etched back to expose a surface of the oxide film on the gate electrode. Thereafter, the oxide films deposited on the side surfaces of the gate electrode are removed to form opening portions. Impurities are implanted to the silicon substrate utilizing the opening portions.

摘要翻译： 1位的存储单元由EEPROM中的1个选择晶体管和1个存储晶体管构成。 源极 - 漏极区之一通常由选择晶体管和存储晶体管使用。 常用的源极 - 漏极区域通过以下步骤制造。 首先，形成晶体管的栅电极。 氧化膜沉积在整个表面上。 将抗蚀剂施加在其上并被回蚀以暴露栅电极上的氧化膜的表面。 此后，去除沉积在栅电极的侧表面上的氧化膜以形成开口部分。 利用开口部分将杂质植入硅衬底。

公开(公告)号：US5798289A

公开(公告)日：1998-08-25

申请号：US716851

申请日：1996-09-10

申请人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

发明人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10817 ,  H01L27/10852

摘要： A method of manufacturing a semiconductor memory device having stacked capacitors is disclosed. After forming a capacitor isolating layer on an insulation layer and forming a contact hole in the insulation layer, a first conductive layer is formed on the insulating layer and the capacitor isolating layer and on an inner surface of the contact hole. The first conductive layer is partially etched and removed by using an etch-back technique to be isolated into a first capacitor portion and a second capacitor portion. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer.

摘要翻译： 公开了一种制造具有层叠电容器的半导体存储器件的方法。 在绝缘层上形成电容器隔离层并在绝缘层中形成接触孔之后，在绝缘层和电容器隔离层上以及接触孔的内表面上形成第一导电层。 通过使用蚀刻技术将第一导电层部分地蚀刻和去除，以将其隔离成第一电容器部分和第二电容器部分。 在第一导电层上形成电介质层。 在介电层上形成第二导电层。

公开(公告)号：US5523596A

公开(公告)日：1996-06-04

申请号：US403614

申请日：1995-03-14

申请人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika

发明人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika

IPC分类号： H01L27/04 ,  H01L21/318 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10808 ,  Y10S438/954

摘要： A capacitor includes a polycrystalline silicon layer 1 as a lower electrode layer, a dielectric layer 112, and a polycrystalline silicon layer 113 as an upper electrode layer. The dielectric layer 112 is formed by an oxynitride film 2, a silicon nitride film 3 and a top oxide film 4. A film thickness t.sub.3 of the top oxide film 4 is controlled to be less than 20 .ANG.. Capacitance of the capacitor can be increased while improving the duration of life of the dielectric layer, resulting in a highly reliable capacitor.

摘要翻译： 电容器包括作为下电极层的多晶硅层1，电介质层112和作为上电极层的多晶硅层113。 电介质层112由氧氮化物膜2，氮化硅膜3和顶部氧化物膜4形成。顶部氧化膜4的膜厚度t3被控制为小于20安培。 可以增加电容器的电容，同时改善电介质层的寿命，导致高度可靠的电容器。

公开(公告)号：US5233212A

公开(公告)日：1993-08-03

申请号：US692395

申请日：1991-04-25

申请人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yasushi Matsui

发明人： Makoto Ohi ,  Hideaki Arima ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Yasushi Matsui

IPC分类号： H01L27/04 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L21/76801 ,  H01L21/76834 ,  H01L27/10808 ,  Y10S257/90

摘要： A semiconductor device includes a plurality of gate electrodes (6a, 6b, 6c, 6d) arranged on the surface of a semiconductor substrate (1) with insulating layers (5, 8) covering the top and the side walls of the gate electrodes. The spaces between the opposing side walls of adjacent gate electrodes on the surface of the element isolation region (2) re smaller than twice the thickness of the thinnest insulating layer (8) among the insulating layers of the side walls of the gate electrodes on the surface of the active regions. The space (14) between the gate electrodes on the element isolation region is filled with the insulating isolation layer (8) so that unevenness in the underlying portion on the element isolation region on which the conductive interconnection layer (10) to be formed is reduced, preventing thinning of the conductive interconnection layer and disconnection due to excessive etching of a resin film in patterning the conductive interconnection layer.

摘要翻译： 半导体器件包括布置在半导体衬底（1）的表面上的多个栅电极（6a，6b，6c，6d），绝缘层（5,8）覆盖了栅电极的顶部和侧壁。 在元件隔离区域（2）的表面上的相邻栅电极的相对侧壁之间的间隔小于栅电极侧壁的绝缘层中最薄绝缘层（8）的厚度的两倍 活性区的表面。 元件隔离区域上的栅电极之间的空间（14）填充有绝缘隔离层（8），使得要形成导电互连层（10）的元件隔离区域上的下面部分的不均匀性减小 防止导电互连层变薄，并且在图案化导电互连层时由于树脂膜的过度蚀刻而导致的断开。

公开(公告)号：US5162262A

公开(公告)日：1992-11-10

申请号：US727032

申请日：1991-07-08

申请人： Natsuo Ajika ,  Hideaki Arima

发明人： Natsuo Ajika ,  Hideaki Arima

IPC分类号： H01L21/285 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532 ,  H01L29/45

CPC分类号： H01L21/76856 ,  H01L21/28518 ,  H01L21/3211 ,  H01L21/76843 ,  H01L23/53223 ,  H01L29/456 ,  H01L2924/0002 ,  Y10S148/019

摘要： An interconnection layer of a semiconductor device according to the present invention has in a contact portion with a conductor layer a multi-layered structure formed from the bottom, of a refractory metal silicide layer, a first refractory metal nitride layer, and a secondary refractory metal nitride layer. Titanium or tungsten is used as a refractory metal. The second refractory metal nitride is formed by thermally nitriding the refractory metal layer. The second refractory metal nitride layer formed by the thermal process has a close packed crystal structure and has an excellent barrier characteristic.

摘要翻译： 根据本发明的半导体器件的互连层具有与难熔金属硅化物层，第一耐火金属氮化物层和第二难熔金属的底部形成的多层结构的导体层的接触部分 氮化物层。 钛或钨用作难熔金属。 通过对耐火金属层进行热氮化而形成第二难熔金属氮化物。 通过热处理形成的第二耐火金属氮化物层具有紧密堆积的晶体结构，并且具有优异的阻挡特性。