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41 条记录 (耗时 0.031 秒)

    Sustain driver, sustain control system, and plasma display
    11.
    发明申请
    Sustain driver, sustain control system, and plasma display 有权
    维持驱动器，维持控制系统和等离子显示器

    公开(公告)号：US20050134533A1

    公开(公告)日：2005-06-23

    申请号：US10991243

    申请日：2004-11-17

    申请人： Masahiko Sasada ,  Hiroki Matsunaga ,  Masashi Inao ,  Hiroshi Ando ,  Jinsaku Kaneda ,  Eisaku Maeda ,  Akihiro Maejima

    发明人： Masahiko Sasada ,  Hiroki Matsunaga ,  Masashi Inao ,  Hiroshi Ando ,  Jinsaku Kaneda ,  Eisaku Maeda ,  Akihiro Maejima

    IPC分类号： G09G3/20 ,  G09G3/291 ,  G09G3/294 ,  G09G3/296 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/06 ,  H01L27/092 ,  H03K17/687 ,  G09G3/28

    CPC分类号： G09G3/296 ,  G09G3/282 ,  G09G3/294 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2330/04

    摘要： The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.

    摘要翻译： 双极晶体管电路的集电极，发射极和基极分别连接到高侧电源端子，电平移位晶体管的漏极和浮动电源端子。 当高边输出晶体管导通时，浮动电源端子处于高电位电源端子的电位。 高侧电源端子通过恒定电压处于高于浮动电源端子的电位的电位。 开启电平移位晶体管时，其漏极电位降低到浮动电源端子的电位以下; 基极电流流过双极晶体管电路，电平移位晶体管的漏极电压钳位在浮动电源端子的电位附近; 双极晶体管电路导通，其集电极电流提供电平移位晶体管的漏极电流。

    Sustain Driver, Sustain Control System, And Display Device
    13.
    发明申请
    Sustain Driver, Sustain Control System, And Display Device 有权
    维持驱动器，维护控制系统和显示设备

    公开(公告)号：US20080068368A1

    公开(公告)日：2008-03-20

    申请号：US11941240

    申请日：2007-11-16

    申请人： Masahiko Sasada ,  Hiroki Matsunaga ,  Masashi Inao ,  Hiroshi Ando ,  Jinsaku Kaneda ,  Eisaku Maeda ,  Akihiro Maejima

    发明人： Masahiko Sasada ,  Hiroki Matsunaga ,  Masashi Inao ,  Hiroshi Ando ,  Jinsaku Kaneda ,  Eisaku Maeda ,  Akihiro Maejima

    IPC分类号： G09G3/28 ,  G09G5/00

    CPC分类号： G09G3/296 ,  G09G3/282 ,  G09G3/294 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2330/04

    摘要： The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.

    摘要翻译： 双极晶体管电路的集电极，发射极和基极分别连接到高侧电源端子，电平移位晶体管的漏极和浮动电源端子。 当高边输出晶体管导通时，浮动电源端子处于高电位电源端子的电位。 高侧电源端子通过恒定电压处于高于浮动电源端子的电位的电位。 开启电平移位晶体管时，其漏极电位降低到浮动电源端子的电位以下; 基极电流流过双极晶体管电路，电平移位晶体管的漏极电压钳位在浮动电源端子的电位附近; 双极晶体管电路导通，其集电极电流提供电平移位晶体管的漏极电流。

    Semiconductor integrated circuit device
    14.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07495296B2

    公开(公告)日：2009-02-24

    申请号：US11139590

    申请日：2005-05-31

    申请人： Eisaku Maeda ,  Akihiro Maejima ,  Hiroki Matsunaga ,  Jinsaku Kaneda ,  Masahiko Sasada

    发明人： Eisaku Maeda ,  Akihiro Maejima ,  Hiroki Matsunaga ,  Jinsaku Kaneda ,  Masahiko Sasada

    IPC分类号： H01L29/94

    CPC分类号： H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to a layout of a multi-channel semiconductor integrated circuit and provides a layout of a semiconductor integrated circuit having ternary circuits in order to increase a degree of integration in the semiconductor integrated circuit and stabilize output characteristics. A ternary circuit is formed by arranging a second high-side transistor, a diode, a second level shift circuit on one hand, and a low-side transistor, a first high-side transistor, a first level shift circuit, and a pre-driver on the other, so that each of cells are arranged in a row and an output bonding pad is placed between the second high-side transistor and the low-side transistor, wherein a cell width of the first level shift circuit, second level shift circuit and pre-driver corresponds to a cell width of the low-side transistor.

    摘要翻译： 本发明涉及多通道半导体集成电路的布局，并提供具有三元电路的半导体集成电路的布局，以增加半导体集成电路中的集成度并稳定输出特性。 一方面通过布置第二高侧晶体管，二极管，第二电平移位电路和低端晶体管，第一高侧晶体管，第一电平移位电路和预置电路来形成三元电路， 驱动器，使得每个单元排列成一行，并且输出接合焊盘放置在第二高侧晶体管和低侧晶体管之间，其中第一电平移位电路的单元宽度，第二电平移位 电路和预驱动器对应于低侧晶体管的单元宽度。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    15.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
    半导体集成电路设备

    公开(公告)号：US20070268059A1

    公开(公告)日：2007-11-22

    申请号：US11749266

    申请日：2007-05-16

    申请人： Tomohisa SAKAGUCHI ,  Hiroki Matsunaga ,  Akihiro Maejima ,  Jinsaku Kaneda ,  Eisaku Maeda

    发明人： Tomohisa SAKAGUCHI ,  Hiroki Matsunaga ,  Akihiro Maejima ,  Jinsaku Kaneda ,  Eisaku Maeda

    IPC分类号： H03L5/00

    CPC分类号： H03K19/00315

    摘要： A semiconductor integrated circuit device capable of securely preventing the output from becoming indefinite even when power is turned ON or OFF or even in a transient state in which the power voltage varies abruptly. In the semiconductor integrated circuit device, a protection circuit compares the power voltage from a first power supply terminal with a reference voltage, detects power ON, power OFF and abrupt power voltage variation, and outputs a reset command signal so that the output at the output terminal has a high impedance at the time of power ON, power OFF and abrupt power voltage variation.

    摘要翻译： 即使电源接通或断开，或即使在电源电压突然变化的过渡状态下，也能够可靠地防止输出变得不确定的半导体集成电路器件。 在半导体集成电路装置中，保护电路将来自第一电源端子的电源电压与参考电压进行比较，检测电源接通，断电和突然的电源电压变化，并输出复位指令信号，使得输出端 端子在电源接通，电源关闭和突然的电源电压变化时具有高阻抗。

    Semiconductor integrated circuit device
    16.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20050263910A1

    公开(公告)日：2005-12-01

    申请号：US11139590

    申请日：2005-05-31

    申请人： Eisaku Maeda ,  Akihiro Maejima ,  Hiroki Matsunaga ,  Jinsaku Kaneda ,  Masahiko Sasada

    发明人： Eisaku Maeda ,  Akihiro Maejima ,  Hiroki Matsunaga ,  Jinsaku Kaneda ,  Masahiko Sasada

    IPC分类号： H01L23/528 ,  H01L27/118 ,  H01L23/52

    CPC分类号： H01L27/11803 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to a layout of a multi-channel semiconductor integrated circuit and provides a layout of a semiconductor integrated circuit having ternary circuits in order to increase a degree of integration in the semiconductor integrated circuit and stabilize the output characteristics. A ternary circuit is formed by arranging a second high-side transistor, a diode, a second level shift circuit on one hand, and a low-side transistor, a first high-side transistor, a first level shift circuit, and a pre-driver on the other, so that each of the cells are arranged in a row and an output bonding pad is placed between the second high-side transistor and the low-side transistor, where a cell width of the first level shift circuit, second level shift circuit and pre-driver corresponds to a cell width of the low-side transistor.

    摘要翻译： 本发明涉及多通道半导体集成电路的布局，并提供具有三元电路的半导体集成电路的布局，以增加半导体集成电路中的集成度并稳定输出特性。 一方面通过布置第二高侧晶体管，二极管，第二电平移位电路和低端晶体管，第一高侧晶体管，第一电平移位电路和预置电路来形成三元电路， 驱动器，使得每个单元格排列成一行，并且输出接合焊盘放置在第二高侧晶体管和低侧晶体管之间，其中第一电平移位电路的单元宽度为第二电平 移位电路和预驱动器对应于低侧晶体管的单元宽度。

    Testing method of semiconductor integrated circuit and information recording medium
    17.
    发明授权
    Testing method of semiconductor integrated circuit and information recording medium 有权
    半导体集成电路和信息记录介质的测试方法

    公开(公告)号：US07719301B2

    公开(公告)日：2010-05-18

    申请号：US12066748

    申请日：2007-03-06

    申请人： Hiromi Tsuchida ,  Akihiro Maejima ,  Jinsaku Kaneda ,  Eisaku Maeda

    发明人： Hiromi Tsuchida ,  Akihiro Maejima ,  Jinsaku Kaneda ,  Eisaku Maeda

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2894

    摘要： A testing method of semiconductor integrated circuit wherein the quality of diffusion for semiconductor chips can be tested before the semiconductor chips become packaged semiconductor integrated circuits is provided. Input data is set, and circuit current values I(L) and I(H) obtained for each of a plurality of circuit areas are compared with first test pass ranges I1(L) and I1(H) to extract articles within the first test pass (S2), and the current values of the circuit areas determined to be articles within the first test pass and second test pass ranges I2(L), and I2(H) determined based on these current values are compared, thereby conducting a retest to extract circuit areas within the second test pass. The current values may be replaced by the voltage values.

    摘要翻译： 提供半导体集成电路的测试方法，其中可以在半导体芯片变成封装半导体集成电路之前测试半导体芯片的扩散质量。 设置输入数据，将与多个电路区域中的每一个获得的电路电流值I（L）和I（H）与第一测试通过范围I1（L）和I1（H）进行比较，以提取第一测试 （S2），并且将根据这些电流值确定的确定为第一测试通过和第二测试通过范围I2（L）和I2（H）的物品的电路区域的当前值进行比较，从而进行重新测试 在第二次测试通过期间提取电路区域。 电流值可以由电压值代替。

    TESTING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND INFORMATION RECORDING MEDIUM
    18.
    发明申请
    TESTING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND INFORMATION RECORDING MEDIUM 有权
    半导体集成电路和信息记录介质的测试方法

    公开(公告)号：US20090237104A1

    公开(公告)日：2009-09-24

    申请号：US12066748

    申请日：2007-03-06

    申请人： Hiromi Tsuchida ,  Akihiro Maejima ,  Jinsaku Kaneda ,  Eisaku Maeda

    发明人： Hiromi Tsuchida ,  Akihiro Maejima ,  Jinsaku Kaneda ,  Eisaku Maeda

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2894

    摘要： A testing method of semiconductor integrated circuit wherein the quality of diffusion for semiconductor chips can be tested before the semiconductor chips become packaged semiconductor integrated circuits is provided. Input data is set, and circuit current values I(L) and I(H) obtained for each of a plurality of circuit areas are compared with first test pass ranges I1(L) and I1(H) to extract articles within the first test pass (S2), and the current values of the circuit areas determined to be articles within the first test pass and second test pass ranges I2(L), and I2(H) determined based on these current values are compared, thereby conducting a retest to extract circuit areas within the second test pass. The current values may be replaced by the voltage values.

    摘要翻译： 提供半导体集成电路的测试方法，其中可以在半导体芯片变成封装半导体集成电路之前测试半导体芯片的扩散质量。 设置输入数据，将与多个电路区域中的每一个获得的电路电流值I（L）和I（H）与第一测试通过范围I1（L）和I1（H）进行比较，以提取第一测试 （S2），并且将根据这些电流值确定的确定为第一测试通过和第二测试通过范围I2（L）和I2（H）的物品的电路区域的当前值进行比较，从而进行重新测试 在第二次测试通过期间提取电路区域。 电流值可以由电压值代替。