公开(公告)号：US20140151702A1

公开(公告)日：2014-06-05

申请号：US14137857

申请日：2013-12-20

申请人： Toru ISHIKAWA

发明人： Toru ISHIKAWA

IPC分类号： H01L21/66

CPC分类号： H01L22/32 ,  H01L22/34 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/15311

摘要： A semiconductor device includes a plurality of signal terminals on each of a plurality of vertically stacked semiconductor chips, each plurality of signal terminals connected to vertically aligned signal terminals of an adjacent semiconductor chip by through silicon vias, a common test terminal on each of the plurality of vertically stacked semiconductor chips connected to a vertically aligned common test terminal of an adjacent semiconductor chip by a through silicon via; a plurality of spiral test terminals on the plurality of vertically stacked semiconductor chips, each spiral test terminal connected to a non-vertically aligned spiral test terminal of an adjacent semiconductor chip by a through silicon via, and a conductive line arranged along a periphery of at least one of the plurality of vertically stacked semiconductor chips, the conductive line connected to a respective common test terminal and a respective spiral test terminal.

摘要翻译： 半导体器件包括在多个垂直堆叠的半导体芯片中的每一个上的多个信号端子，每个多个信号端子通过硅通孔连接到相邻半导体芯片的垂直排列的信号端子，多个信号端子中的每一个上的公共测试端子 通过硅通孔连接到相邻半导体芯片的垂直对准的公共测试端子的垂直堆叠半导体芯片; 在多个垂直堆叠的半导体芯片上的多个螺旋测试端子，每个螺旋测试端子通过硅通孔连接到相邻半导体芯片的非垂直排列螺旋测试端子，以及沿着周边设置的导线 多个垂直堆叠的半导体芯片中的至少一个，连接到相应的公共测试端子的导线和相应的螺旋测试端子。

公开(公告)号：US20110199851A1

公开(公告)日：2011-08-18

申请号：US13028862

申请日：2011-02-16

申请人： Kunihiko KATO ,  Toru ISHIKAWA

发明人： Kunihiko KATO ,  Toru ISHIKAWA

IPC分类号： G11C8/18

CPC分类号： G11C5/148 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  Y02D10/14

摘要： A memory system includes a clock generation circuit, a memory device, and a controller. The memory device includes output circuits and a temperature sensor, the output circuits configured to output data at an output timing obtained based on a clock signal supplied from the clock generation circuit. The controller includes input circuits that receive the data outputted from the memory device at an input timing obtained based on a clock signal supplied from the clock generation circuit and a correction value setting circuit that adjusts the input timing based on a temperature value from the temperature sensor.

摘要翻译： 存储器系统包括时钟产生电路，存储器件和控制器。 所述存储装置包括输出电路和温度传感器，所述输出电路经配置以基于从所述时钟发生电路提供的时钟信号获得的输出定时输出数据。 该控制器包括输入电路，该输入电路基于从时钟发生电路提供的时钟信号获得的输入定时接收从存储器件输出的数据，以及校正值设置电路，其基于来自温度传感器的温度值调节输入定时 。

公开(公告)号：US20110148464A1

公开(公告)日：2011-06-23

申请号：US12969030

申请日：2010-12-15

申请人： Toru HATAKEYAMA ,  Toru ISHIKAWA

发明人： Toru HATAKEYAMA ,  Toru ISHIKAWA

IPC分类号： H03K19/0175

CPC分类号： H03K19/0027 ,  G11C5/06 ,  G11C7/1087

摘要： A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.

摘要翻译： 半导体器件包括调整逻辑阈值电压的第一输入缓冲器，第一复制电路，第一参考电压产生电路和第一比较器电路。 第一复制电路在电路配置与第一输入缓冲器相同。 第一个复制电路具有连接到输入的输入和输出。 第一个复制电路产生逻辑阈值电压作为输出电压。 第一参考电压产生电路产生第一参考电压。 第一比较器电路将逻辑阈值电压作为第一复制电路的输出电压与第一参考电压进行比较，以产生第一阈值调整信号。 第一比较器电路将第一阈值调整信号提供给第一输入缓冲器和第一复制电路。 第一阈值调整信号允许第一输入缓冲器调整逻辑阈值电压。

公开(公告)号：US20090316510A1

公开(公告)日：2009-12-24

申请号：US12488086

申请日：2009-06-19

申请人： Toru ISHIKAWA ,  Sachiko KAMISAKI

发明人： Toru ISHIKAWA ,  Sachiko KAMISAKI

IPC分类号： G11C7/00 ,  G11C8/18 ,  G11C8/00

CPC分类号： G11C7/1078 ,  G11C7/1045 ,  G11C7/109 ,  G11C29/12015 ,  G11C29/14 ,  G11C2207/107

摘要： Control information needed for executing data transmission/reception through a data terminal is received via its own control terminal in a first operation mode, and the control information is received by using the own control terminal and also a control terminal of at least one of the other ports in a second operation mode.

摘要翻译： 通过数据终端执行数据发送/接收所需的控制信息经由其自己的控制终端以第一操作模式被接收，并且控制信息通过使用自己的控制终端以及至少另一个的控制终端来接收 端口处于第二操作模式。

公开(公告)号：US20090303806A1

公开(公告)日：2009-12-10

申请号：US12261851

申请日：2008-10-30

申请人： Sachiko EDO ,  Toru ISHIKAWA

发明人： Sachiko EDO ,  Toru ISHIKAWA

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C29/14 ,  G11C29/12015

摘要： A semiconductor memory device may include,.but is not limited to, a storing unit and a selecting unit. The storing unit stores serial input data at at least one of a first type edge and a second type edge of a clock signal. The selecting unit receives the input data from the storing unit. The selecting unit selects the input data. The selecting unit outputs the selected input data in parallel.

摘要翻译： 半导体存储器件可以包括但不限于存储单元和选择单元。 存储单元以时钟信号的第一类型边缘和第二类型边缘中的至少一个存储串行输入数据。 选择单元从存储单元接收输入数据。 选择单元选择输入数据。 选择单元并行地输出所选择的输入数据。

公开(公告)号：US20160013695A1

公开(公告)日：2016-01-14

申请号：US14436503

申请日：2013-02-15

申请人： Toru ISHIKAWA ,  Yoshiro IMAZAWA

发明人： Toru ISHIKAWA ,  Yoshiro IMAZAWA

IPC分类号： H02K3/34

CPC分类号： H02K3/345 ,  H02K3/325 ,  H02K3/528

摘要： There is provided a rotor of a rotating electrical machine including a pair of field core bodies that are provided so as to enclose the field coil via the insulation bobbin around which the field coil is wound, in which a claw-shaped magnetic pole extending from an outer circumferential section of the field core body in an axial direction is provided on the field core body. The insulation bobbin has a plurality of flange sections extending from the base section of the claw-shaped magnetic pole along an inner surface of the claw-shaped magnetic pole of the field core body, and a plurality of thin portions are formed in the root section of the flange section at intervals in a circumferential direction.

摘要翻译： 提供了一种旋转电机的转子，其包括一对场磁芯体，其被设置成通过其上缠绕有励磁线圈的绝缘筒管包围励磁线圈，其中从 场芯体的轴向的外周部设在场芯体上。 绝缘筒管具有多个凸缘部，该凸缘部从爪状磁极的基部沿着磁芯体的爪状磁极的内表面延伸，并且在根部形成有多个薄部 的凸缘部分沿圆周方向间隔开。

公开(公告)号：US20130076387A1

公开(公告)日：2013-03-28

申请号：US13608138

申请日：2012-09-10

申请人： Toru ISHIKAWA ,  Machio SEGAWA

发明人： Toru ISHIKAWA ,  Machio SEGAWA

IPC分类号： H01L23/48 ,  G01R31/26

CPC分类号： G11C29/025 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2924/13091 ,  H01L2924/00

摘要： In a semiconductor device in which semiconductor chips having a number of signal TSVs are stacked, a huge amount of man-hours have been required to perform a continuity test for each of the signal TSVs. According to the present invention, no continuity test is performed directly on signal TSVs. Dummy bumps are arranged in addition to signal TSVs. The dummy bumps of the semiconductor chips are connected through a conduction path that can pass the dummy bumps between the semiconductor chips with one stroke when the semiconductor chips are stacked. A continuity test of the conduction path allows a bonding defect on bonded surfaces of two of the stacked semiconductor chips to be measured and detected.

摘要翻译： 在其中堆叠具有多个信号TSV的半导体芯片的半导体器件中，需要大量的工时来对每个信号TSV执行连续性测试。 根据本发明，直接对信号TSV进行连续性测试。 除了信号TSV之外还布置了虚设的凸块。 当半导体芯片堆叠时，半导体芯片的虚设凸起通过导电路径连接，导电路径能够使半导体芯片之间的虚设凸块通过一行。 传导路径的连续性测试允许测量和检测两个堆叠半导体芯片的接合表面上的接合缺陷。

公开(公告)号：US20130049223A1

公开(公告)日：2013-02-28

申请号：US13587724

申请日：2012-08-16

申请人： Keisuke NOMOTO ,  Toru ISHIKAWA

发明人： Keisuke NOMOTO ,  Toru ISHIKAWA

IPC分类号： H01L23/48

CPC分类号： H01L23/5384 ,  G11C5/02 ,  G11C5/04 ,  G11C11/4093 ,  G11C2207/105 ,  H01L21/50 ,  H01L23/538 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562

摘要： The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips are connected to each other via a plurality of through electrodes. Each of the chips includes a plurality of TSV array portions provided so as to correspond to a plurality of channels. The TSV array portions include a TSV array portion that contributes to an input and an output depending upon the number of the chips being stacked, and a pass-through TSV array portion that is not connected to an input/output circuit.

公开(公告)号：US20100058104A1

公开(公告)日：2010-03-04

申请号：US12547863

申请日：2009-08-26

申请人： Toru ISHIKAWA

发明人： Toru ISHIKAWA

IPC分类号： G06F1/04

CPC分类号： G06F1/06 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  G11C7/222 ,  H04L7/02 ,  H04L7/033

摘要： To provide a semiconductor device including a data input circuit and a data output circuit connected to a plurality of data input/output terminals, where at least one of the data input circuit and the data output circuit fetches data in response to multi-phase clock signals having different phases to be timing signals for fetching data, and adjusts a valid range for fetching data to be substantially uniform for each of the multi-phase clock signals. According to the present invention, the window width of data can be made uniform by individually adjusting the multi-phase clock signals that are input or output timing signals, and thus characteristics of the semiconductor device can be improved.

摘要翻译： 为了提供包括数据输入电路和数据输出电路的半导体器件，连接到多个数据输入/输出端子，其中数据输入电路和数据输出电路中的至少一个响应于多相时钟信号而取出数据 具有不同的相位作为用于取出数据的定时信号，并且调整用于将数据取出的有效范围对于每个多相时钟信号基本上是一致的。 根据本发明，可以通过单独调整作为输入或输出定时信号的多相时钟信号来使数据的窗口宽度均匀，从而可以提高半导体器件的特性。

公开(公告)号：US20080247261A1

公开(公告)日：2008-10-09

申请号：US12061717

申请日：2008-04-03

申请人： Toru ISHIKAWA

发明人： Toru ISHIKAWA

IPC分类号： G11C8/18 ,  G11C8/10

CPC分类号： G11C7/1078 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

摘要： A semiconductor memory device includes: a command latch circuit that latches a command signal; an address latch circuit that latches an address signal; a mode latch circuit that latches a mode signal; and a command decoder that selects the address latch circuit in response to the latch of a normal command by the command latch circuit, and selects the mode latch circuit in response to the latch of an adjustment command. With this arrangement, the mode signal can be dynamically received without performing a mode register set. Therefore, when a sufficiently large latch margin of the mode latch circuit is secured, there is no risk that it becomes impossible to input the mode signal.

摘要翻译： 半导体存储器件包括：锁存命令信号的命令锁存电路; 锁存地址信号的地址锁存电路; 锁存模式信号的模式锁存电路; 以及命令解码器，其响应于由命令锁存电路的正常命令的锁存而选择地址锁存电路，并且响应于调整命令的锁存而选择模式锁存电路。 通过这种布置，可以动态地接收模式信号而不执行模式寄存器组。 因此，当确保模式锁存电路的足够大的锁存边沿时，不会有不能输入模式信号的风险。