公开(公告)号：US5117382A

公开(公告)日：1992-05-26

申请号：US618114

申请日：1990-11-26

申请人： Hideo Maejima ,  Takashi Hotta ,  Ikuro Masuda ,  Masahiro Iwamura ,  Kouzaburou Kurita ,  Masahiro Ueno

发明人： Hideo Maejima ,  Takashi Hotta ,  Ikuro Masuda ,  Masahiro Iwamura ,  Kouzaburou Kurita ,  Masahiro Ueno

IPC分类号： G06F5/01 ,  G06F7/50 ,  G06F7/508 ,  G06F13/40 ,  G06F15/78

CPC分类号： G06F7/508 ,  G06F13/4077 ,  G06F15/7832 ,  G06F5/015 ,  G06F2207/3872 ,  Y02B60/1207 ,  Y02B60/1225 ,  Y02B60/1228 ,  Y02B60/1235

摘要： A semiconductor integrated circuit is provided for performing an arithmetic operation using an arithmetic operation circuit. The integrated circuit includes a read bus for connecting the arithmetic operation circuit with a plurality of registers which store input data and/or output data of said arithmetic operation circuit. A precharge and sense circuit connects said arithmetic operation circuit to said read bus. The precharge and sense circuit includes a precharge circuit to precharge the read bus to a first level before the read operation, and a sense circuit to detect that the level of the read bus has discharged to a second, lower level after the read operation begins. In this way, the integrated circuit can detect very slight potential variations on said read bus.

公开(公告)号：US4849658A

公开(公告)日：1989-07-18

申请号：US81696

申请日：1987-08-04

申请人： Masahiro Iwamura ,  Takashi Hotta ,  Hideo Maejima

发明人： Masahiro Iwamura ,  Takashi Hotta ,  Hideo Maejima

IPC分类号： H03K19/08 ,  G06F7/50 ,  G06F7/501 ,  G11C7/12 ,  H03K19/096 ,  H03K19/177

CPC分类号： G06F7/5016 ,  G11C7/12 ,  H03K19/0963 ,  H03K19/1772 ,  G06F2207/3872

摘要： A dynamic logic circuit is provided which is arranged to realize high speed operation. At least one bipolar transistor is provided having a collector, a base and an emitter, with the collector-emitter current path connected between the output of the dynamic logic circuit and a first potential. A precharging device is coupled between a second potential and the output of the dynamic logic circuit to precharge the output according to at least one clock signal which periodically changes its state. Further, at least two field-effect transistors are provided, wherein one assumes an on or off state opposite to that of the precharging means in response to the clock signal while the other operates in response to at least one input signal. The two field-effect transistors have their source-drain current paths connected between the output of the dynamic logic circuit and the base of the bipolar transistor.

摘要翻译： 提供了一种实现高速运行的动态逻辑电路。 提供至少一个具有集电极，基极和发射极的双极晶体管，其中集电极 - 发射极电流路径连接在动态逻辑电路的输出端和第一电位之间。 预充电装置耦合在第二电位和动态逻辑电路的输出端之间，以根据周期性地改变其状态的至少一个时钟信号对输出进行预充电。 此外，提供了至少两个场效应晶体管，其中响应于时钟信号而假定与预充电装置相反的导通或截止状态，而另一个响应于至少一个输入信号而工作。 两个场效应晶体管的源极 - 漏极电流路径连接在动态逻辑电路的输出端和双极晶体管的基极之间。

公开(公告)号：US07111187B2

公开(公告)日：2006-09-19

申请号：US10701447

申请日：2003-11-06

申请人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

发明人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

IPC分类号： G06F1/04

CPC分类号： H03K5/1565 ,  G06F1/10 ,  H03L7/18

摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.

摘要翻译： 一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生 与原始时钟信号K锁相并且具有预定占空比的至少一个第二时钟信号K 1 1和其操作时序被第二时钟信号K _{1 <1>，并且由至少一对逻辑器件之间提供的接口的操作时序由时钟信号K 1 1同步地控制。}

公开(公告)号：US06256726B1

公开(公告)日：2001-07-03

申请号：US07979772

申请日：1992-11-20

申请人： Takashi Hotta ,  Shigeya Tanaka ,  Hideo Maejima

发明人： Takashi Hotta ,  Shigeya Tanaka ,  Hideo Maejima

IPC分类号： G06F938

CPC分类号： G06F9/3889 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3885

摘要： The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machine cycle at a time are processed in parallel by the plurality of arithmetic operation units.

摘要翻译： 用于由管线系统执行由有线逻辑实现的指令的数据处理器包括多个指令寄存器和相同数量的算术运算单元。 一次在一个机器周期中在指令寄存器中读取的多个指令由多个算术运算单元并行处理。

公开(公告)号：US5680637A

公开(公告)日：1997-10-21

申请号：US599856

申请日：1996-02-13

申请人： Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Hiromichi Yamada ,  Hideo Maejima

发明人： Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Hiromichi Yamada ,  Hideo Maejima

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/30189 ,  G06F9/30043 ,  G06F9/30079 ,  G06F9/38 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3853 ,  G06F9/3885

摘要： A RISC processor is arranged to reduce a code size, make the hardware less complicated, execute a plurality of operations for one machine cycle, and enhance the performance. The processor is capable of executing N instruction each having a short word length for indicating a single operation or an instruction having a long word length for indicating M (N

摘要翻译： RISC处理器被设置为减少代码大小，使硬件更不复杂，对一个机器周期执行多个操作，并提高性能。 处理器能够执行每个具有用于指示单个操作的短字长的N指令或具有用于指示M（N

公开(公告)号：US5542083A

公开(公告)日：1996-07-30

申请号：US460601

申请日：1995-06-02

申请人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

发明人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

IPC分类号： G06F1/10 ,  H03K5/156 ,  H03L7/18 ,  G06F1/04

CPC分类号： H03K5/1565 ,  G06F1/10 ,  H03L7/18

摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controllled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

摘要翻译： 一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生 至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件，以及设置在第二时钟信号K之间的接口的操作定时 至少一对逻辑器件由时钟信号K1同步控制。

公开(公告)号：US5274829A

公开(公告)日：1993-12-28

申请号：US114720

申请日：1987-10-28

申请人： Takashi Hotta ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh ,  Hideo Maejima

发明人： Takashi Hotta ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh ,  Hideo Maejima

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F15/78 ,  G06F1/00

CPC分类号： G06F9/268 ,  G06F9/26 ,  G06F9/328

摘要： A data processing apparatus which allows a large number of micro instructions to be read at high speeds by storing frequently used micro instructions in the on-chip ROM and those less frequently used in the off-chip memory. From the address of the micro instruction to be accessed, it is determined whether the micro instruction is stored in the on-chip ROM or the off-chip memory, and the micro instruction is accessed on the basis of this determination. A cache memory may also be provided on the chip for providing high speed repeat access to micro instructions stored in the off-chip memory.

摘要翻译： 一种数据处理装置，其通过将经常使用的微指令存储在片上ROM中以及在片外存储器中较少使用的微指令，允许以高速读取大量微指令。 根据要访问的微指令的地址，确定微指令是存储在片上ROM还是片外存储器中，并且基于该确定来访问微指令。 还可以在芯片上提供高速缓冲存储器，以提供对存储在片外存储器中的微指令的高速重复访问。

公开(公告)号：US09127599B2

公开(公告)日：2015-09-08

申请号：US14009631

申请日：2011-04-08

申请人： Masahiko Masubuchi ,  Takashi Hotta

发明人： Masahiko Masubuchi ,  Takashi Hotta

IPC分类号： F02D19/08 ,  F02D19/10 ,  F02D15/04 ,  F02D15/00 ,  F02B43/00 ,  F02B43/10

CPC分类号： F02D19/081 ,  F02B43/00 ,  F02B2043/103 ,  F02D13/0234 ,  F02D13/0269 ,  F02D15/00 ,  F02D15/04 ,  F02D19/027 ,  F02D19/0647 ,  F02D19/0692 ,  F02D19/08 ,  F02D19/10 ,  F02D19/105 ,  F02D41/0025 ,  Y02T10/142 ,  Y02T10/36

摘要： The present invention is intended to suppress an excessive increase in the amount of emission of HC in a multi-fuel internal combustion engine of compression ignition type which is able to perform mixed combustion of a liquid fuel, which can be ignited by compression, and a gas fuel which has methane as a primary component. In the present invention, a required mixing ratio of the liquid fuel and the gas fuel as well as a required amount of HC emission is calculated based on an operating state of the multi-fuel internal combustion engine (S103, S104). Then, based on the required mixing ratio and the required amount of HC emission, a required compression ratio is calculated which is a compression ratio at which an amount of HC emission from the multi-fuel internal combustion engine becomes the required amount of HC emission (S105), and the compression ratio of the multi-fuel internal combustion engine is controlled to the required compression ratio (S107).

摘要翻译： 本发明旨在抑制能够进行可压缩点燃的液体燃料的混合燃烧的压缩点火式多燃料内燃机中HC的排放量的过度增加，以及 以甲烷为主要成分的燃气。 在本发明中，基于多燃料内燃机的运转状态来计算液体燃料和气体燃料的所需混合比以及所需的HC排放量（S103，S104）。 然后，基于所需的混合比和所需的HC排放量，计算所需的压缩比，其是来自多燃料内燃机的HC排放量成为所需HC排放量的压缩比（ S105），将多燃料内燃机的压缩比控制为所需的压缩比（S107）。

公开(公告)号：US20140025277A1

公开(公告)日：2014-01-23

申请号：US14009631

申请日：2011-04-08

申请人： Masahiko Masubuchi ,  Takashi Hotta

发明人： Masahiko Masubuchi ,  Takashi Hotta

IPC分类号： F02D19/10

CPC分类号： F02D19/081 ,  F02B43/00 ,  F02B2043/103 ,  F02D13/0234 ,  F02D13/0269 ,  F02D15/00 ,  F02D15/04 ,  F02D19/027 ,  F02D19/0647 ,  F02D19/0692 ,  F02D19/08 ,  F02D19/10 ,  F02D19/105 ,  F02D41/0025 ,  Y02T10/142 ,  Y02T10/36

摘要： The present invention is intended to suppress an excessive increase in the amount of emission of HC in a multi-fuel internal combustion engine of compression ignition type which is able to perform mixed combustion of a liquid fuel, which can be ignited by compression, and a gas fuel which has methane as a primary component. In the present invention, a required mixing ratio of the liquid fuel and the gas fuel as well as a required amount of HC emission is calculated based on an operating state of the multi-fuel internal combustion engine (S103, S104). Then, based on the required mixing ratio and the required amount of HC emission, a required compression ratio is calculated which is a compression ratio at which an amount of HC emission from the multi-fuel internal combustion engine becomes the required amount of HC emission (S105), and the compression ratio of the multi-fuel internal combustion engine is controlled to the required compression ratio (S107).

摘要翻译： 本发明旨在抑制能够进行可压缩点燃的液体燃料的混合燃烧的压缩点火式多燃料内燃机中HC的排放量的过度增加，以及 以甲烷为主要成分的燃气。 在本发明中，基于多燃料内燃机的运转状态来计算液体燃料和气体燃料的所需混合比以及所需的HC排放量（S103，S104）。 然后，基于所需的混合比和所需的HC排放量，计算所需的压缩比，其是来自多燃料内燃机的HC排放量成为所需HC排放量的压缩比（ S105），将多燃料内燃机的压缩比控制为所需的压缩比（S107）。

公开(公告)号：US07557809B2

公开(公告)日：2009-07-07

申请号：US10983757

申请日：2004-11-09

申请人： Yasuhiro Nakatsuka ,  Tetsuya Shimomura ,  Manabu Jyou ,  Yuichiro Morita ,  Takashi Hotta ,  Kazushige Yamagishi ,  Yutaka Okada

发明人： Yasuhiro Nakatsuka ,  Tetsuya Shimomura ,  Manabu Jyou ,  Yuichiro Morita ,  Takashi Hotta ,  Kazushige Yamagishi ,  Yutaka Okada

IPC分类号： G06F13/14 ,  G09G5/39 ,  G06F15/167

CPC分类号： G09G5/39 ,  G09G2360/125

摘要： The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

摘要翻译： 多媒体数据处理系统的基本部分包括CPU 1100，图像显示单元2100，统一存储器1200，系统总线1920和连接到系统总线的设备1300,1400和1500。 在这种配置中，CPU形成在安装在包括指令处理单元1110和显示控制单元1140的单个硅晶片上的LSI上。主存储区域1210和显示区域1220存储在统一存储器内。 与用于连接LSI和输入/输出设备的系统总线无关地提供用于连接对应的LSI和统一存储器的统一存储器端口1910。 统一的存储器端口可以比系统总线更快地驱动。