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    Multipath accessible semiconductor memory device with host interface between processors
    11.
    发明授权
    Multipath accessible semiconductor memory device with host interface between processors 有权
    多路径可访问的半导体存储器件，具有处理器之间的主机接口

    公开(公告)号：US07941612B2

    公开(公告)日：2011-05-10

    申请号：US11829859

    申请日：2007-07-27

    Applicant: Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Dong-Hyuk Lee ,  Jong-Wook Park ,  Ho-Cheol Lee ,  Mi-Jo Kim ,  Jung-Sik Kim ,  Chang-Ho Lee

    Inventor： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Dong-Hyuk Lee ,  Jong-Wook Park ,  Ho-Cheol Lee ,  Mi-Jo Kim ,  Jung-Sik Kim ,  Chang-Ho Lee

    IPC: G06F12/00

    CPC classification number: G11C7/1075 ,  G11C7/1012 ,  G11C11/4096

    Abstract: A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

    Abstract translation: 多路可及半导体存储器件提供处理器之间的接口功能。 存储器设备可以包括具有可操作地耦合到两个或更多个端口的共享存储器区域的存储单元阵列，该两个或多个端口可由两个或多个处理器独立地访问;访问路径形成单元，用于在一个端口和共享之间形成数据访问路径 响应于由处理器施加的外部信号的存储区域以及具有信号量区域和由两个或多个处理器在共享存储器区域中可访问的邮箱区域的接口单元，以提供用于两个或多个处理器之间的通信的接口功能。

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME
    12.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME 有权
    具有它的半导体存储器件和存储器系统

    公开(公告)号：US20100322021A1

    公开(公告)日：2010-12-23

    申请号：US12788029

    申请日：2010-05-26

    Applicant: Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

    Inventor： Ho-Young Kim ,  Ho-Cheol Lee ,  Jung-Bae Lee

    IPC: G11C7/00 ,  G11C8/18

    CPC classification number: G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/222 ,  G11C2207/2272

    Abstract: A semiconductor memory device is disclosed. The semiconductor device includes a memory cell array, a clock signal generator configured to receive an external clock signal from the outside of the memory device and output an internal clock signal, and a data output unit configured to receive an internal data signal from the memory cell array and output a read data signal in response to the internal clock signal. The semiconductor memory device also includes a read data strobe unit configured to output a read data strobe signal having a cycle time of n times (n is an integer equal to or more than 2) a cycle time of the internal clock signal, based on the internal clock signal.

    Abstract translation: 公开了一种半导体存储器件。 半导体器件包括存储单元阵列，时钟信号发生器，被配置为从存储器件的外部接收外部时钟信号并输出​​内部时钟信号;以及数据输出单元，被配置为从存储器单元接收内部数据信号 阵列并响应于内部时钟信号输出读取数据信号。 半导体存储器件还包括读取数据选通单元，其被配置为基于内部时钟信号的周期时间，输出具有n倍（n是等于或大于2的整数）的周期时间的读取数据选通信号 内部时钟信号。

    Auto-precharge control circuit in semiconductor memory and method thereof
    13.
    发明授权
    Auto-precharge control circuit in semiconductor memory and method thereof 有权
    半导体存储器中的自动预充电控制电路及其方法

    公开(公告)号：US07355912B2

    公开(公告)日：2008-04-08

    申请号：US10268732

    申请日：2002-10-11

    Applicant: Sang-Kyun Park ,  Ho-Cheol Lee

    Inventor： Sang-Kyun Park ,  Ho-Cheol Lee

    IPC: G11C7/00

    CPC classification number: G11C11/4076 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4094 ,  G11C2207/229

    Abstract: An auto-precharge control circuit in a semiconductor memory and method thereof, where the auto-precharge starting point may vary. The auto-precharge starting point may vary in response to at least one control signal. The auto-precharge starting point may vary in accordance with frequency and/or latency information. The auto-precharge starting point may vary in response to at least one control signal including clock frequency information. The auto-precharge starting point may vary depending on a latency signal received from a mode register setting command.

    Abstract translation: 半导体存储器中的自动预充电控制电路及其方法，其中自动预充电起点可以变化。 自动预充电起始点可以响应于至少一个控制信号而变化。 自动预充电起始点可以根据频率和/或延迟信息而变化。 响应于包括时钟频率信息的至少一个控制信号，自动预充电起始点可以变化。 自动预充电起点可以根据从模式寄存器设置命令接收到的等待时间信号而变化。

    Integrated circuit memory devices having selectable column addressing and methods of operating same
    15.
    发明授权
    Integrated circuit memory devices having selectable column addressing and methods of operating same 失效
    具有可选择列寻址的集成电路存储器件及其操作方法

    公开(公告)号：US06438063B1

    公开(公告)日：2002-08-20

    申请号：US09714302

    申请日：2000-11-16

    Applicant: Ho-Cheol Lee

    Inventor： Ho-Cheol Lee

    IPC: G06F1206

    CPC classification number: G11C7/225 ,  G11C7/1018 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C2207/2281

    Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平是第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的去激活信号，使得响应于激活信号的所选存储器组在活动周期中工作，而未被选择的存储器组响应于 灭活信号在预充电循环中工作。

    Synchronous semiconductor memory device with a write latency control function
    16.
    发明授权
    Synchronous semiconductor memory device with a write latency control function 失效
    具有写延迟控制功能的同步半导体存储器件

    公开(公告)号：US5568445A

    公开(公告)日：1996-10-22

    申请号：US397690

    申请日：1995-03-02

    Applicant: Churoo Park ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Hyun-Soon Jang

    Inventor： Churoo Park ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Hyun-Soon Jang

    IPC: G11C11/407 ,  G11C7/00 ,  G11C7/22 ,  G11C11/408 ,  G11C8/00

    CPC classification number: G11C7/22

    Abstract: A semiconductor memory device for processing data in synchronization with a system clock applied from the exterior includes a circuit for generating a write latency control signal, a circuit for generating one active information enlarged signal from a plurality of active information signals generated in response to a column related control signal supplied from the exterior, and a circuit for holding internal operations of a column address counter, a burst length counter and a data transfer switching circuit for a prescribed time in which the active information enlarged signal is in an active state.

    Abstract translation: 一种用于与从外部施加的系统时钟同步地处理数据的半导体存储器件包括用于产生写等待时间控制信号的电路，用于根据响应于列产生的多个有效信息信号产生一个有源信息放大信号的电路 以及用于保持列地址计数器，脉冲串长度计数器和数据传输切换电路的内部操作的电路，其中有效信息放大信号处于活动状态的规定时间。

    Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating for delay time of transmission line
    17.
    发明授权
    Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating for delay time of transmission line 有权
    具有芯片间连接单元的堆叠存储器件，包括其的存储器系统以及补偿传输线路的延迟时间的方法

    公开(公告)号：US08929118B2

    公开(公告)日：2015-01-06

    申请号：US13080061

    申请日：2011-04-05

    Applicant: Chi-Sung Oh ,  Jin-Ho Kim ,  Ho-Cheol Lee ,  Uk-Song Kang ,  Hoon Lee

    Inventor： Chi-Sung Oh ,  Jin-Ho Kim ,  Ho-Cheol Lee ,  Uk-Song Kang ,  Hoon Lee

    IPC: G11C5/06 ,  G11C5/02 ,  G11C7/10

    CPC classification number: G11C7/10 ,  G11C5/02 ,  G11C7/1048

    Abstract: A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.

    Abstract translation: 提供一种叠层半导体存储器件，其包括第一存储器芯片，该第一存储器芯片包括第一传输线，第二传输线和被配置为对第一传输线的第一信号执行逻辑运算的逻辑电路和第二传输线的第二信号 传输线。 层叠半导体存储器件还包括堆叠在第一存储器芯片上的第二存储器芯片，电连接在第二存储器芯片和第一存储器芯片的第一传输线之间的芯片间连接单元，以及虚拟芯片间连接单元 电耦合到第一存储器芯片的第二传输线并且与第二存储器芯片电隔离。

    Semiconductor device
    19.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08396682B2

    公开(公告)日：2013-03-12

    申请号：US12900547

    申请日：2010-10-08

    Applicant: Chi-Sung Oh ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

    Inventor： Chi-Sung Oh ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

    IPC: G01R27/28 ,  G06F19/00

    CPC classification number: G01R31/2884 ,  G01R31/31726

    Abstract: A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.

    Abstract translation: 提供半导体器件。 半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。 通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。 从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

    Multiprocessor system and method thereof
    20.
    发明申请
    Multiprocessor system and method thereof 审中-公开

    公开(公告)号：US20110107006A1

    公开(公告)日：2011-05-05

    申请号：US12929222

    申请日：2011-01-10

    Applicant: Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

    Inventor： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

    IPC: G06F12/00

    CPC classification number: G06F12/02

    Abstract: A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

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