利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

51 条记录 (耗时 0.022 秒)

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20110093235A1

    公开(公告)日：2011-04-21

    申请号：US12900547

    申请日：2010-10-08

    申请人： CHI-SUNG OH ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

    发明人： CHI-SUNG OH ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

    IPC分类号： G01R31/14 ,  H03L7/00

    CPC分类号： G01R31/2884 ,  G01R31/31726

    摘要： A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.

    摘要翻译： 提供半导体器件。 半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。 通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。 从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

    Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating for delay time of transmission line
    4.
    发明授权
    Stacked memory device having inter-chip connection unit, memory system including the same, and method of compensating for delay time of transmission line 有权
    具有芯片间连接单元的堆叠存储器件，包括其的存储器系统以及补偿传输线路的延迟时间的方法

    公开(公告)号：US08929118B2

    公开(公告)日：2015-01-06

    申请号：US13080061

    申请日：2011-04-05

    申请人： Chi-Sung Oh ,  Jin-Ho Kim ,  Ho-Cheol Lee ,  Uk-Song Kang ,  Hoon Lee

    发明人： Chi-Sung Oh ,  Jin-Ho Kim ,  Ho-Cheol Lee ,  Uk-Song Kang ,  Hoon Lee

    IPC分类号： G11C5/06 ,  G11C5/02 ,  G11C7/10

    CPC分类号： G11C7/10 ,  G11C5/02 ,  G11C7/1048

    摘要： A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.

    摘要翻译： 提供一种叠层半导体存储器件，其包括第一存储器芯片，该第一存储器芯片包括第一传输线，第二传输线和被配置为对第一传输线的第一信号执行逻辑运算的逻辑电路和第二传输线的第二信号 传输线。 层叠半导体存储器件还包括堆叠在第一存储器芯片上的第二存储器芯片，电连接在第二存储器芯片和第一存储器芯片的第一传输线之间的芯片间连接单元，以及虚拟芯片间连接单元 电耦合到第一存储器芯片的第二传输线并且与第二存储器芯片电隔离。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08396682B2

    公开(公告)日：2013-03-12

    申请号：US12900547

    申请日：2010-10-08

    申请人： Chi-Sung Oh ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

    发明人： Chi-Sung Oh ,  Dong-Hyuk Lee ,  Ho-Cheol Lee ,  Jang-Woo Ryu ,  Jung-Bae Lee

    IPC分类号： G01R27/28 ,  G06F19/00

    CPC分类号： G01R31/2884 ,  G01R31/31726

    摘要： A semiconductor device is provided. The semiconductor device applies data applied through a bump pad on which a bump is mounted through a test pad to a test apparatus such that the reliability of the test can be improved. The amount of test pads is significantly reduced by allowing data output through bump pads to be selectively applied to a test pad. Data and signals applied from test pads are synchronized with each other and applied to bump pads during a test operation such that the reliability of the test can be improved without the need of an additional test chip.

    摘要翻译： 提供半导体器件。 半导体器件将通过测试焊盘安装有凸块的凸块焊盘施加的数据施加到测试装置，使得可以提高测试的可靠性。 通过允许通过凸块焊盘的数据输出被选择性地施加到测试焊盘，测试焊盘的量显着减少。 从测试焊盘施加的数据和信号彼此同步，并在测试操作期间应用于凸块焊盘，从而可以提高测试的可靠性，而无需额外的测试芯片。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD THEREFOR
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD THEREFOR 失效
    半导体存储器件及其方法

    公开(公告)号：US20070171755A1

    公开(公告)日：2007-07-26

    申请号：US11616846

    申请日：2006-12-27

    申请人： Chi-Sung OH ,  Ho-Cheol Lee ,  Nam-Jong Kim

    发明人： Chi-Sung OH ,  Ho-Cheol Lee ,  Nam-Jong Kim

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C11/406 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/12 ,  G11C11/40603 ,  G11C11/40618

    摘要： A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.

    摘要翻译： 提供一种半导体存储器件及其方法，用于根据外部命令和刷新模式改变访问共享存储区域的访问权限。 在一个实施例中，半导体存储器件包括用于输入用于第一或第二模式刷新操作的命令信号的多个输入/输出端口，被分成多个不同存储区域的存储器阵列，该存储器阵列包括至少可访问的共享存储器区域 多个输入/输出端口中的两个，以及用于响应于外部命令信号分配访问共享存储器区域的访问权限的授权控制块。 授权控制块还可以生成授权控制信号，用于优先地分配访问共享存储器区域的访问权限到输入/输出端口，以输入用于第一模式刷新操作的命令信号。

    STACKED MEMORY DEVICE HAVING INTER-CHIP CONNECTION UNIT, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF COMPENSATING FOR DELAY TIME OF TRANSMISSION LINE
    7.
    发明申请
    STACKED MEMORY DEVICE HAVING INTER-CHIP CONNECTION UNIT, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF COMPENSATING FOR DELAY TIME OF TRANSMISSION LINE 有权
    具有片间连接单元的堆叠存储器件，包括其的存储器系统以及传输线延迟时间补偿方法

    公开(公告)号：US20110249483A1

    公开(公告)日：2011-10-13

    申请号：US13080061

    申请日：2011-04-05

    申请人： Chi-Sung Oh ,  Jin-Ho Kim ,  Ho-Cheol Lee ,  Uk-Song Kang ,  Hoon Lee

    发明人： Chi-Sung Oh ,  Jin-Ho Kim ,  Ho-Cheol Lee ,  Uk-Song Kang ,  Hoon Lee

    IPC分类号： G11C5/06 ,  G11C7/00

    CPC分类号： G11C7/10 ,  G11C5/02 ,  G11C7/1048

    摘要： A stacked semiconductor memory device is provided which includes a first memory chip including a first transmission line, a second transmission line, and a logic circuit configured to execute a logic operation on a first signal of the first transmission line and a second signal of the second transmission line. The stacked semiconductor memory device further includes a second memory chip stacked over the first memory chip, an inter-chip connection unit electrically coupled between the second memory chip and the first transmission line of the first memory chip, and a dummy inter-chip connection unit electrically coupled to the second transmission line of the first memory chip and electrically isolated from the second memory chip.

    摘要翻译： 提供一种叠层半导体存储器件，其包括第一存储器芯片，该第一存储器芯片包括第一传输线，第二传输线和被配置为对第一传输线的第一信号执行逻辑运算的逻辑电路和第二传输线的第二信号 传输线。 层叠半导体存储器件还包括堆叠在第一存储器芯片上的第二存储器芯片，电连接在第二存储器芯片和第一存储器芯片的第一传输线之间的芯片间连接单元，以及虚拟芯片间连接单元 电耦合到第一存储器芯片的第二传输线并且与第二存储器芯片电隔离。

    Multi-port semiconductor memory device and method for accessing and refreshing the same
    8.
    发明授权
    Multi-port semiconductor memory device and method for accessing and refreshing the same 失效
    多端口半导体存储器件及其访问和刷新方法

    公开(公告)号：US07394711B2

    公开(公告)日：2008-07-01

    申请号：US11616846

    申请日：2006-12-27

    申请人： Chi-Sung Oh ,  Ho-Cheol Lee ,  Nam-Jong Kim

    发明人： Chi-Sung Oh ,  Ho-Cheol Lee ,  Nam-Jong Kim

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C7/1075 ,  G11C8/10 ,  G11C8/12 ,  G11C11/40603 ,  G11C11/40618

    摘要： A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.

    摘要翻译： 提供一种半导体存储器件及其方法，用于根据外部命令和刷新模式改变访问共享存储区域的访问权限。 在一个实施例中，半导体存储器件包括用于输入用于第一或第二模式刷新操作的命令信号的多个输入/输出端口，被分成多个不同存储区域的存储器阵列，该存储器阵列包括至少可访问的共享存储器区域 多个输入/输出端口中的两个，以及用于响应于外部命令信号分配访问共享存储器区域的访问权限的授权控制块。 授权控制块还可以生成授权控制信号，用于优先地分配访问共享存储器区域的访问权限到输入/输出端口，以输入用于第一模式刷新操作的命令信号。

    Multiprocessor system and method thereof
    10.
    发明授权
    Multiprocessor system and method thereof 有权
    多处理器系统及其方法

    公开(公告)号：US07870326B2

    公开(公告)日：2011-01-11

    申请号：US11819601

    申请日：2007-06-28

    申请人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

    发明人： Yun-Hee Shin ,  Han-Gu Sohn ,  Young-Min Lee ,  Ho-Cheol Lee ,  Soo-Young Kim ,  Dong-Hyuk Lee ,  Chang-Ho Lee

    IPC分类号： G06F12/00

    CPC分类号： G06F12/02

    摘要： A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port.

    摘要翻译： 提供了一种多处理器系统及其方法。 示例性多处理器系统可以包括第一和第二处理器，具有存储单元阵列的动态随机存取存储器，所述存储单元阵列包括通过第一端口耦合到第一处理器的第一存储器组，耦合到第二存储器组的第二存储器组和第四存储器组 处理器通过第二端口和通过第一和第二端口与第一和第二处理器共享并连接的第三存储器组，以及用于分配存储体地址以选择单独地选择第一和第二存储体的存储体地址分配单元，如同样的 通过第一和第二端口的存储器地址，使得第一和第二存储器组的起始地址在引导中变得相等，并且通过第一和第二端口分配存储体地址以选择第三存储体作为不同的存储体地址， 通过第二个端口，银行地址选择第四个存储器，作为与银行地址相同的银行地址，选择第三个存储器 银行通过第一个港口。