公开(公告)号：US07747833B2

公开(公告)日：2010-06-29

申请号：US11643850

申请日：2006-12-22

申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim

发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim

IPC分类号： G06F12/00

CPC分类号： G06F13/4022 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/408

摘要： Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

摘要翻译： 提供了具有多个存储体和多个链接控制器的存储器系统。 对于每个存储体，存在用于接收每个链路控制器的输出并且仅将一个链路控制器的输出传递到存储体的第一切换逻辑。 对于每个链路控制器，存在用于接收每个存储体的输出并且仅将一个存储体的输出传递到链路控制器的第二切换逻辑。 根据本发明的实施例，存在用于控制第一开关逻辑和第二开关逻辑的操作的开关控制器逻辑，以防止多个链路控制器同时或重叠地访问同一存储体，并且用于防止同时或重叠访问 通过相同的链路控制器到多个银行。

公开(公告)号：US20100091538A1

公开(公告)日：2010-04-15

申请号：US12533732

申请日：2009-07-31

申请人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

发明人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

IPC分类号： G11C5/02 ,  G11C7/00 ,  G11C5/06

CPC分类号： G11C5/02 ,  G06F13/4234 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/15311

摘要： Bridge device architecture for connecting discrete memory devices is disclosed. A bridge device is used in conjunction with a composite memory device including at least one discrete memory device. The bridge device comprises a local control interface connected to the at least one discrete memory device, a local input/output interface connected to the at least one discrete memory device, and a global input/output interface interposed between the local control interface and the local input/output interface. The global input/output interface receives and provides global memory control signals and also receives and provides write data to and read data from the at least one discrete memory device.

摘要翻译： 公开了用于连接分立存储器件的桥接器件架构。 桥接器件与包括至少一个分立存储器件的复合存储器件结合使用。 桥接器件包括连接到至少一个分立存储器件的本地控制接口，连接到至少一个分立存储器件的本地输入/输出接口以及插入在本地控制接口和本地之间的全局输入/输出接口 输入/输出接口。 全局输入/输出接口接收并提供全局存储器控制信号，并且还接收并向至少一个离散存储器件提供写入数据和从其读取数据。

公开(公告)号：US20080209110A1

公开(公告)日：2008-08-28

申请号：US12030235

申请日：2008-02-13

申请人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

发明人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

IPC分类号： G06F12/02 ,  G06F12/16

CPC分类号： G06F13/4243 ,  G06F13/4247

摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.

摘要翻译： 提供了一种页面编程操作的装置和方法。 当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本 。 在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。 由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

公开(公告)号：US08626958B2

公开(公告)日：2014-01-07

申请号：US13077168

申请日：2011-03-31

申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

IPC分类号： G06F3/00

CPC分类号： G11C16/20 ,  G11C8/12

摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. In cases of different device types being separately provided to the interconnected devices, sequential IDs are generated in each of the different device types and also the total number of each device type are recognized. In a case of a “don't care” code is provided to the interconnected devices, sequential IDs are generated and also, the total number of the interconnected devices is recognized, regardless of the type differences.

摘要翻译： 多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND，NOR和AND型闪存）串联连接。 每个设备都有其设备类型的设备类型信息。 包含在串行输入（SI）中的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。 生成的ID被传送到串行互连的另一个设备。 在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。 在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。 在将不同设备类型分别提供给互连设备的情况下，在不同设备类型中的每一种中生成顺序ID，并且还识别每种设备类型的总数。 在向互连设备提供“不关心”代码的情况下，生成顺序ID，并且还识别互连设备的总数，而不管类型差异。

公开(公告)号：US08285960B2

公开(公告)日：2012-10-09

申请号：US13077122

申请日：2011-03-31

申请人： Hong Beom Pyeon ,  Hakjune Oh ,  Jin-Ki Kim

发明人： Hong Beom Pyeon ,  Hakjune Oh ,  Jin-Ki Kim

IPC分类号： G06F12/00

CPC分类号： G06F13/4022 ,  G11C7/1048 ,  G11C7/18 ,  G11C11/408

摘要： Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

摘要翻译： 提供了具有多个存储体和多个链接控制器的存储器系统。 对于每个存储体，存在用于接收每个链路控制器的输出并且仅将一个链路控制器的输出传递到存储体的第一切换逻辑。 对于每个链路控制器，存在用于接收每个存储体的输出并且仅将一个存储体的输出传递到链路控制器的第二切换逻辑。 根据本发明的实施例，存在用于控制第一开关逻辑和第二开关逻辑的操作的开关控制器逻辑，以防止多个链路控制器同时或重叠地访问同一存储体，并且用于防止同时或重叠访问 通过相同的链路控制器到多个银行。

公开(公告)号：US08271758B2

公开(公告)日：2012-09-18

申请号：US11622828

申请日：2007-01-12

申请人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim

发明人： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim

IPC分类号： G06F12/00 ,  G06F3/00

CPC分类号： G06F13/4243 ,  G06F12/0676

摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR-, AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input are fed to one device of the serial interconnection configuration. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.

摘要翻译： 多个混合型存储器件（例如，DRAM，SRAM，MRAM和NAND-，NOR-，AND-型闪存）被串联连接。 每个设备都有其设备类型的设备类型信息。 串行输入中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连配置的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。 生成的ID被传送到串行互连的另一个设备。 在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。 在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。

公开(公告)号：US08230147B2

公开(公告)日：2012-07-24

申请号：US12784238

申请日：2010-05-20

申请人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC分类号： G06F13/00 ,  G06F1/12 ,  G06F12/00 ,  G11C7/00

CPC分类号： G11C7/10 ,  G06F13/1689

摘要： A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection and a memory location. The target device responds to the read command to read data in the location identified by the memory location. Read data is provided as an output signal that is transmitted from a last device in the serial interconnection to a data receiver of the controller. The data receiver establishes acquisition instants relating to clocks in consideration of a total flow-through latency in the serial interconnection. Where each device has a clock synchronizer, a propagated clock signal through the serial interconnection is used for establishing the acquisition instants. The read data is latched in response to the established acquisition instants in consideration of the flow-through latency, valid data is latched in the data receiver.

摘要翻译： 系统控制器与串行互连中的设备通信。 系统控制器发送读取命令，标识串行互连中的目标设备的设备地址和存储器位置。 目标设备响应读取命令以读取由存储器位置识别的位置中的数据。 读取数据被提供为从串行互连中的最后一个设备发送到控制器的数据接收器的输出信号。 考虑到串行互连中的总流通延迟，数据接收器建立与时钟有关的采集时刻。 在每个设备具有时钟同步器的情况下，通过串行互连的传播时钟信号用于建立采集时刻。 考虑到流通延迟，响应于建立的采集时刻来读取数据被锁存，有效数据被锁存在数据接收器中。

公开(公告)号：US08199598B2

公开(公告)日：2012-06-12

申请号：US12882931

申请日：2010-09-15

申请人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

发明人： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC分类号： G11C7/00

CPC分类号： G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

摘要翻译： 公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。 在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。 在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。 闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

公开(公告)号：US20110153974A1

公开(公告)日：2011-06-23

申请号：US13038997

申请日：2011-03-02

申请人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

发明人： Jin-Ki Kim ,  HakJune Oh ,  Hong Beom Pyeon

IPC分类号： G06F12/00

CPC分类号： G06F13/4239 ,  G11C16/08 ,  G11C16/20 ,  G11C2216/30

摘要： A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.

摘要翻译： 提供了存储器系统结构，其中存储器控制器控制串行互连配置中的存储器件。 存储器控制器具有用于发送存储器命令的输出端口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入端口。 每个存储器件包括诸如NAND型闪存，NOR型闪速存储器，随机存取存储器和静态随机存取存储器之类的存储器。 每个存储器命令特定于目标存储器件的存储器类型。 存储器命令和存储器响应的数据路径由互连提供。 给定的存储器命令遍历存储器件以达到其串行互连配置的预期存储器件。 在其接收时，预期的存储器件执行给定的存储器命令，并且如果适当的话，向下一个存储器件发送存储器响应。 存储器响应被传送到存储器控制器。

公开(公告)号：US07908429B2

公开(公告)日：2011-03-15

申请号：US12832121

申请日：2010-07-08

申请人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

发明人： Hong Beom Pyeon ,  Jin-Ki Kim ,  HakJune Oh

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F3/00 ,  G06F5/00

CPC分类号： G06F13/4243 ,  G06F13/4247

摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.