利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

52 条记录 (耗时 0.018 秒)

    Memory devices using tri-state buffers to discharge data lines, and methods of operating same
    11.
    发明授权
    Memory devices using tri-state buffers to discharge data lines, and methods of operating same 失效
    使用三态缓冲器来释放数据线的存储器件，以及操作方法

    公开(公告)号：US07254061B2

    公开(公告)日：2007-08-07

    申请号：US11153508

    申请日：2005-06-15

    申请人： Sang-Wan Nam ,  Seung-Keun Lee

    发明人： Sang-Wan Nam ,  Seung-Keun Lee

    IPC分类号： G11C16/00

    CPC分类号： G11C16/26 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106

    摘要： A memory device includes a sense amplifier circuit, a tri-state buffer, a data latch circuit and a data line. The sense amplifier circuit senses and amplifies a current of a memory cell. The tri-state buffer receives an output of the sense amplifier circuit. The data latch circuit latches an output of the tri-state buffer. The data line connects the tri-state buffer and the data latch circuit. The memory device removes charge on the data line using a latch enable signal, which is applied to the tri-state buffer before a read operation.

    摘要翻译： 存储器件包括读出放大器电路，三态缓冲器，数据锁存电路和数据线。 感测放大器电路感测并放大存储器单元的电流。 三态缓冲器接收读出放大器电路的输出。 数据锁存电路锁存三态缓冲器的输出。 数据线连接三态缓冲器和数据锁存电路。 存储器件使用锁存使能信号去除数据线上的电荷，该信号在读取操作之前被施加到三态缓冲器。

    Multi level flash memory device and program method
    12.
    发明授权
    Multi level flash memory device and program method 失效
    多级闪存设备和程序方法

    公开(公告)号：US07054199B2

    公开(公告)日：2006-05-30

    申请号：US11021181

    申请日：2004-12-22

    申请人： Seung-Keun Lee ,  Dong-Ho Park

    发明人： Seung-Keun Lee ,  Dong-Ho Park

    IPC分类号： G11C11/34 ,  G11C16/06

    CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

    摘要： We describe a multi level flash memory device and program method. The multi level flash memory device includes a plurality of memory cells, each storing an amount of charge indicative of more than two possible states and control circuitry coupled to the memory cells. The control circuitry to applying a programming voltage alternating with a verification voltage to the memory cells until all are at a desired state and applying at least one additional programming voltage to the cells in a highest state without applying a verification voltage. The method includes applying at least one programming pulse to the cells, verifying that each cell has reached the desired state, selecting the cells that are programmed for a highest state, and applying at least one additional programming pulse to the selected cells without further verifying their state.

    摘要翻译： 我们描述一个多级闪存设备和程序方法。 多级闪存器件包括多个存储器单元，每个存储器单元存储指示多于两种可能状态的电荷量以及耦合到存储器单元的控制电路。 控制电路，用于将编程电压与验证电压交替地施加到存储器单元，直到全部处于期望状态，并且在不施加验证电压的情况下以最高状态向单元施加至少一个附加编程电压。 该方法包括向单元施加至少一个编程脉冲，验证每个单元已经达到期望状态，选择被编程为最高状态的单元，以及向选定单元施加至少一个附加编程脉冲，而不进一步验证它们 州。

    Non-volatile semiconductor memory device
    13.
    发明申请
    Non-volatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US20050078523A1

    公开(公告)日：2005-04-14

    申请号：US10922122

    申请日：2004-08-18

    申请人： Seung-Won Lee ,  Seung-Keun Lee

    发明人： Seung-Won Lee ,  Seung-Keun Lee

    IPC分类号： G11C16/06 ,  G11C7/06 ,  G11C7/18 ,  G11C16/02 ,  G11C16/04 ,  G11C16/26 ,  G11C16/28 ,  G11C29/24 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

    CPC分类号： G11C7/062 ,  G11C7/18 ,  G11C16/04 ,  G11C16/28 ,  G11C29/24 ,  G11C29/50004

    摘要： A memory device in accordance with embodiments of the present invention includes a reference cell array and a plurality of banks. Each of the banks includes memory cells. A plurality of current copier circuits corresponds to the banks, respectively. Each of the current copier circuits copies a reference current flowing through a reference cell array to generate a reference voltage. A plurality of sense blocks correspond to the banks, respectively. Each of the sense blocks includes a plurality of sense amplifiers for sensing data from a corresponding bank in response to the reference voltage from the corresponding current copier circuit. Memory cell lay-out area is reduced, and sense speed is increased.

    摘要翻译： 根据本发明的实施例的存储器件包括参考单元阵列和多个存储体。 每个银行都包含存储单元。 多个当前复印机电路分别对应于存储体。 每个当前复印机电路复制流过参考单元阵列的参考电流以产生参考电压。 多个感测块分别对应于存储体。 每个感测块包括多个读出放大器，用于响应于来自相应的当前复印机电路的参考电压来感测来自相应存储体的数据。 存储单元布局区域减少，感测速度提高。

    Flash memory device with cell current measuring scheme using write driver
    15.
    发明授权
    Flash memory device with cell current measuring scheme using write driver 失效

    公开(公告)号：US06654290B2

    公开(公告)日：2003-11-25

    申请号：US09995500

    申请日：2001-11-26

    申请人： Seung-Keun Lee ,  Young-Ho Lim

    发明人： Seung-Keun Lee ,  Young-Ho Lim

    IPC分类号： G11C1606

    CPC分类号： G11C29/12005 ,  G11C16/04 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5006

    摘要： A flash memory device includes a column selector, a voltage switch circuit, and a plurality of write drivers. The column selector selects one of bitlines of each group, and the voltage switch circuit selects a program voltage from a high voltage pump circuit or an external voltage from an external voltage pad. The write drivers are connected to input/output pads through corresponding data input buffers. For a test operation mode to measure a cell current, each of the write drivers transfers or cuts off a voltage, selected by the voltage switch circuit, to a selected bitline of a corresponding group in response to a data bit signal applied to a corresponding input/output pad. Thus, the write drivers are used to measure a cell current of a memory cell without extra path gates.

    Semiconductor memory having embedding lockable cells
    16.
    发明授权
    Semiconductor memory having embedding lockable cells 失效
    半导体存储器具有嵌入式可锁定单元

    公开(公告)号：US5920504A

    公开(公告)日：1999-07-06

    申请号：US928488

    申请日：1997-09-12

    申请人： Seung-Keun Lee ,  Jin-Seon Yeom

    发明人： Seung-Keun Lee ,  Jin-Seon Yeom

    IPC分类号： G11C16/02 ,  G11C14/00 ,  G11C16/04 ,  G11C16/22

    CPC分类号： G11C16/22

    摘要： A semiconductor memory is disclosed having lockable cells which can be programmed or erased to store the information of an erasure lock or an erasure unlock without disturbing data stored in memory cells. The memory includes a memory cell array formed of a plurality of blocks, the blocks formed of a plurality of memory cells which are coupled to a plurality of memory word lines and bit lines, a lockable cell array formed of a plurality of lockable cells which are coupled to a lockable bit line and a plurality of lockable word lines which are electrically isolated from the memory word lines, and a lockable decoding circuit to generate a plurality of decoding signals to select the lockable word lines independent upon a selection of the memory word lines.

    摘要翻译： 公开了一种半导体存储器，其具有可编程或擦除的可锁定单元，以存储擦除锁定信息或擦除解锁，而不会干扰存储在存储单元中的数据。 所述存储器包括由多个块形成的存储单元阵列，所述存储单元阵列由耦合到多个存储器字线和位线的多个存储器单元形成，由多个可锁定单元形成的可锁定单元阵列， 耦合到可锁定位线和与存储器字线电隔离的多个可锁定字线;以及可锁定解码电路，用于产生多个解码信号，以独立于存储器字线的选择来选择可锁定字线 。

    Charge pump circuit operating responsive to a mode
    17.
    发明授权
    Charge pump circuit operating responsive to a mode 失效
    电荷泵电路响应于模式运行

    公开(公告)号：US07427888B2

    公开(公告)日：2008-09-23

    申请号：US10888667

    申请日：2004-07-08

    申请人： Pyung-Moon Zhang ,  Seung-Keun Lee

    发明人： Pyung-Moon Zhang ,  Seung-Keun Lee

    IPC分类号： G05F1/10

    CPC分类号： H02M3/073

    摘要： Disclosed is a charge pump circuit that operates responsive to a test or general operation mode. The charge pump circuit includes at least one charge pump part. A voltage level sensing block generates a level sensing signal by sensing an output voltage. An oscillator generates complementary pulse signals responsive to the level sensing signal. And a selecting circuit block generates a selected voltage that is one of a high voltage and a supply voltage to the at least one charge pump part, the high voltage having a level higher than the supply voltage.

    摘要翻译： 公开了一种响应于测试或一般操作模式操作的电荷泵电路。 电荷泵电路包括至少一个电荷泵部分。 电压电平检测块通过检测输出电压来产生电平检测信号。 振荡器响应于电平感测信号产生互补的脉冲信号。 并且选择电路块产生对至少一个电荷泵部分的高电压和电源电压之一的选定电压，高电压具有高于电源电压的电平。

    Row decoder circuit for use in non-volatile memory device
    18.
    发明授权
    Row decoder circuit for use in non-volatile memory device 有权
    行解码器电路用于非易失性存储器件

    公开(公告)号：US07286411B2

    公开(公告)日：2007-10-23

    申请号：US11167984

    申请日：2005-06-27

    申请人： Jin-Sung Park ,  Myong-Jae Kim ,  Seung-Keun Lee

    发明人： Jin-Sung Park ,  Myong-Jae Kim ,  Seung-Keun Lee

    IPC分类号： G11C16/06 ,  G11C8/00 ,  G11C5/06

    CPC分类号： G11C8/08 ,  G11C16/08

    摘要： The invention disclosed herein is a non-volatile memory device. The non-volatile memory device comprises: a first transistor connected between a first voltage and a control node, and controlled by a second voltage; a second transistor connected between the first voltage and the control node, and controlled by a third voltage, and a word line driver for driving a word line in responsive to a voltage of the control node. The second voltage is set to a ground voltage during an erase operation. The third voltage is set to a power voltage during the erase operation.

    摘要翻译： 本文公开的发明是非易失性存储器件。 非易失性存储器件包括：连接在第一电压和控制节点之间并由第二电压控制的第一晶体管; 连接在第一电压和控制节点之间并由第三电压控制的第二晶体管，以及用于响应于控制节点的电压驱动字线的字线驱动器。 在擦除操作期间将第二电压设置为接地电压。 在擦除操作期间将第三电压设置为电源电压。

    Methods of program verifying non-volatile memory devices
    19.
    发明申请
    Methods of program verifying non-volatile memory devices 失效
    程序验证非易失性存储器件的方法

    公开(公告)号：US20060126391A1

    公开(公告)日：2006-06-15

    申请号：US11241291

    申请日：2005-09-30

    申请人： Bo-Geun Kim ,  Seung-Keun Lee

    发明人： Bo-Geun Kim ,  Seung-Keun Lee

    IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C11/34

    CPC分类号： G11C16/3436

    摘要： Methods of verifying a program state may be provided for a non-volatile memory device including a multi-bit memory cell transistor providing more than two different program states. More particularly, the multi-bit memory cell transistor may be programmed from a first program state to a second program state, and a reference memory cell corresponding to the second program state may be selected. After programming the multi-bit memory cell transistor to the second program state and after selecting the reference memory cell corresponding to the second program state, a current flowing through the multi-bit memory cell transistor programmed to the second memory state and a current flowing through the reference memory cell may be compared. Programming the multi-bit memory cell transistor to the second program state may then be verified responsive to comparing the currents flowing through the multi-bit memory cell and the reference memory cell.

    摘要翻译： 可以为包括提供多于两个不同程序状态的多位存储单元晶体管的非易失性存储器件提供验证程序状态的方法。 更具体地，可以将多位存储单元晶体管从第一编程状态编程到第二编程状态，并且可以选择与第二编程状态相对应的参考存储单元。 在将多位存储单元晶体管编程到第二编程状态之后，并且在选择与第二编程状态相对应的参考存储单元之后，流过被编程到第二存储器状态的多位存储单元晶体管中的电流和流过第 可以比较参考存储单元。 响应于比较流过多位存储器单元和参考存储单元的电流，可以将多位存储单元晶体管编程到第二编程状态。

    Memory devices using tri-state buffers to discharge data lines, and methods of operating same
    20.
    发明申请
    Memory devices using tri-state buffers to discharge data lines, and methods of operating same 失效
    使用三态缓冲器来释放数据线的存储器件，以及操作方法

    公开(公告)号：US20060092716A1

    公开(公告)日：2006-05-04

    申请号：US11153508

    申请日：2005-06-15

    申请人： Sang-Wan Nam ,  Seung-Keun Lee

    发明人： Sang-Wan Nam ,  Seung-Keun Lee

    IPC分类号： G11C7/10

    CPC分类号： G11C16/26 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106

    摘要： A memory device includes a sense amplifier circuit, a tri-state buffer, a data latch circuit and a data line. The sense amplifier circuit senses and amplifies a current of a memory cell. The tri-state buffer receives an output of the sense amplifier circuit. The data latch circuit latches an output of the tri-state buffer. The data line connects the tri-state buffer and the data latch circuit. The memory device removes charge on the data line using a latch enable signal, which is applied to the tri-state buffer before a read operation.

    摘要翻译： 存储器件包括读出放大器电路，三态缓冲器，数据锁存电路和数据线。 感测放大器电路感测并放大存储器单元的电流。 三态缓冲器接收读出放大器电路的输出。 数据锁存电路锁存三态缓冲器的输出。 数据线连接三态缓冲器和数据锁存电路。 存储器件使用锁存使能信号去除数据线上的电荷，该信号在读取操作之前被施加到三态缓冲器。