公开(公告)号：US20240178051A1

公开(公告)日：2024-05-30

申请号：US18524355

申请日：2023-11-30

Applicant: IMEC VZW

Inventor： Anabela Veloso ,  Rongmei Chen ,  An De Keersgieter ,  Geert Eneman ,  Philippe Matagne

IPC: H01L21/74 ,  H01L21/768

CPC classification number: H01L21/743 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76879 ,  H01L21/823431

Abstract: A method includes: forming a structure on a frontside of a substrate, the structure including a first and a second source/drain body located in a first and a second source/drain region, respectively, and a channel body including a channel layer extending between the first and second source/drain bodies; forming a trench beside the first source/drain region by etching the substrate such that a lower portion of the trench undercuts the first source/drain region; forming a liner on the trench; forming an opening in the liner underneath the first source/drain region; and forming a dummy interconnect in the trench; where the method further includes exposing the dummy interconnect from a backside of the substrate; removing the dummy interconnect selectively to the liner; and forming a buried interconnect of a conductive material in the trench, where the buried interconnect is connected to the first source/drain body via the opening in the liner.

公开(公告)号：US20230080522A1

公开(公告)日：2023-03-16

申请号：US17932582

申请日：2022-09-15

Applicant: IMEC VZW

Inventor： Eric Beyne ,  Anne Jourdain ,  Anabela Veloso

IPC: H01L23/528 ,  H01L23/522

Abstract: An integrated circuit (IC) chip is provided. In one aspect, a semiconductor substrate includes active devices on its front surface and power delivery tracks on its back surface. The active devices are powered through mutually parallel buried power rails, with the power delivery tracks running transversely with respect to the power rails, and connected to the power rails by a plurality of Through Semiconductor Via connections, which run from the power rails to the back of the substrate. The TSVs are elongate slit-shaped TSVs aligned to the power rails and arranged in a staggered pattern, so that any one of the power delivery tracks is connected to a first row of mutually parallel TSVs, and any power delivery track directly adjacent to the power delivery track is connected to another row of TSVs which are staggered relative to the TSVs of the first row. A method of producing an IC chip includes producing the slit-shaped TSVs before the buried power rails.

公开(公告)号：US20210336057A1

公开(公告)日：2021-10-28

申请号：US17241318

申请日：2021-04-27

Applicant: IMEC VZW

Inventor： Geert Eneman ,  Basoene Briggs ,  An De Keersgieter ,  Anabela Veloso ,  Paola Favia

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor structure comprises a semiconductor substrate having a top layer and one or more semiconductor monocrystalline nanostructures. Each nanostructure has a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a distance, and a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The source and drain structures are made of a p-doped (or alternatively n-doped) semiconductor monocrystalline material having a smaller (or alternatively larger) unstrained lattice constant than the unstrained lattice constant of the semiconductor monocrystalline material making the semiconductor monocrystalline nanostructure on which they are grown, thereby creating compressive (or alternatively tensile) strain in that semiconductor monocrystalline nanostructure.

公开(公告)号：US20190198643A1

公开(公告)日：2019-06-27

申请号：US16220361

申请日：2018-12-14

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Anabela Veloso ,  Efrain Altamirano Sanchez ,  Zheng Tao

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/3065

CPC classification number: H01L29/66666 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/42372 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a vertical channel device and a method of fabricating the same. According to one aspect, a method for fabricating a vertical channel device includes forming a vertical semiconductor structure including an upper portion, an intermediate portion and a lower portion, by etching a semiconductor layer stack arranged on a substrate. The semiconductor layer stack includes an upper semiconductor layer, an intermediate semiconductor layer and a lower semiconductor layer, wherein the intermediate semiconductor layer is formed of a material different from a material of the lower semiconductor layer and different from a material of the upper semiconductor layer. Forming the vertical semiconductor structure includes: etching the upper semiconductor layer to form the upper portion and the intermediate semiconductor layer to form the intermediate portion, detecting whether the etching has reached the lower semiconductor layer, and in response to detecting that the etching has reached the lower semiconductor layer, changing to a modified etching chemistry being different from an etching chemistry used during the etching of the intermediate semiconductor layer, and etching the lower semiconductor layer using the modified etching chemistry to form the lower portion. The modified etching chemistry is such that the lower portion is formed to present, along at least a part of the lower portion, a lateral dimension gradually increasing along a direction towards the substrate. The method further comprises forming a gate stack extending vertically along the intermediate portion to define a channel region of the vertical channel device.

公开(公告)号：US09972622B2

公开(公告)日：2018-05-15

申请号：US15152700

申请日：2016-05-12

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Anabela Veloso

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823885 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/165 ,  H01L29/7848

Abstract: A method for manufacturing a CMOS device includes providing a semiconductor base layer epitaxially growing a germanium layer on the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed. The method also includes performing an anneal step, thinning the germanium layer and patterning the germanium layer into fin structures or into vertical wire structures. The method further includes laterally embedding the fin structures or vertical wire structures in a dielectric layer and providing a masking layer covering the first region, leaving the second region exposed. The method yet further includes selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench and growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench.

公开(公告)号：US11201093B2

公开(公告)日：2021-12-14

申请号：US16836653

申请日：2020-03-31

Applicant: IMEC vzw

Inventor： Anabela Veloso ,  Trong Huynh Bao ,  Julien Ryckaert ,  Raf Appeltans

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.

公开(公告)号：US20190081156A1

公开(公告)日：2019-03-14

申请号：US16119132

申请日：2018-08-31

Applicant: IMEC VZW

Inventor： Anabela Veloso ,  Geert Eneman ,  Nadine Collaert ,  Erik Rosseel

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08

Abstract: A device and method for forming a vertical channel device is disclosed. The method includes: forming a vertical semiconductor pillar on a substrate, the vertical semiconductor pillar including a first pillar section, a second pillar section and a third pillar section, wherein the second pillar section is arranged between the first pillar section and the third pillar section and wherein the second pillar section is formed of a material being different from a material forming an upper portion of the first pillar section and different from a material forming a lower portion of the third pillar section; forming a spacer layer on a peripheral surface of the upper portion of the first pillar section and on a peripheral surface of the lower portion of the third pillar section; and forming a gate stack embedding the second pillar section and said upper portion of the first pillar section and said lower portion of the third pillar section, wherein the spacer layer forms a spacer between the gate stack and said upper portion of the first pillar section and between the gate stack and said lower portion of the third pillar section.

公开(公告)号：US20170358586A1

公开(公告)日：2017-12-14

申请号：US15349904

申请日：2016-11-11

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Trong Huynh Bao ,  Anabela Veloso ,  Julien Ryckaert

IPC: H01L27/11 ,  H01L29/423 ,  H01L23/528 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L27/0688 ,  H01L27/1104 ,  H01L29/0676 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/78642 ,  H01L29/7869

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to semiconductor devices having a stacked arrangement, and further relates to methods of fabricating such devices. In one aspect, a semiconductor device comprises a first memory device and a second memory device formed over a substrate and at least partly stacked in a vertical direction. Each of the first and second memory devices has a plurality of vertical transistors, wherein each vertical transistor has a vertical channel extending in the vertical direction.

公开(公告)号：US20160336317A1

公开(公告)日：2016-11-17

申请号：US15152700

申请日：2016-05-12

Applicant: IMEC VZW

Inventor： Liesbeth Witters ,  Anabela Veloso

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823885 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/165 ,  H01L29/7848

Abstract: A method for manufacturing a CMOS device includes providing a semiconductor base layer epitaxially growing a germanium layer on the semiconductor base layer, the germanium layer having thickness above a critical thickness such that an upper portion of the germanium layer is strain relaxed. The method also includes performing an anneal step, thinning the germanium layer and patterning the germanium layer into fin structures or into vertical wire structures. The method further includes laterally embedding the fin structures or vertical wire structures in a dielectric layer and providing a masking layer covering the first region, leaving the second region exposed. The method yet further includes selectively removing the fin structure or vertical wire structure in the second region up until the main upper surface, resulting in a trench and growing a protrusion in the trench by epitaxially growing one or more semiconductor layers in the trench.

Abstract translation: 一种用于制造CMOS器件的方法包括提供在半导体基底层上外延生长锗层的半导体基底层，所述锗层的厚度高于临界厚度，使得锗层的上部应力松弛。 该方法还包括执行退火步骤，使锗层变薄并将锗层图案化成翅片结构或垂直线结构。 该方法还包括将鳍结构或垂直线结构横向嵌入介电层中，并提供覆盖第一区的掩蔽层，使第二区露出。 该方法还包括选择性地去除第二区域中的翅片结构或垂直线结构，直到主上表面，产生沟槽并通过在沟槽中外延生长一个或多个半导体层而在沟槽中生长突起。