公开(公告)号：US20230187539A1

公开(公告)日：2023-06-15

申请号：US18063859

申请日：2022-12-09

Applicant: IMEC VZW

Inventor： Sujith Subramanian ,  Hans Mertens ,  Steven Demuynck

IPC: H01L29/66 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/1033 ,  H01L29/66545

Abstract: A method for forming a first transistor structure from a first channel layer and a second transistor structure from a second channel layer is disclosed. The first channel layer and the second channel layer are vertically stacked on a substrate. The method includes processing the first transistor structure from above, followed by processing the second transistor structure from the backside.

公开(公告)号：US20230187528A1

公开(公告)日：2023-06-15

申请号：US18065122

申请日：2022-12-13

Applicant: IMEC VZW

Inventor： Sujith Subramanian ,  Steven Demuynck ,  Hans Mertens

IPC: H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66439 ,  H01L29/0673 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/66545

Abstract: The disclosed method includes forming an initial layer stack comprising a sacrificial layer of a first semiconductor material and over the sacrificial layer a channel layer of a second semiconductor material, forming a fin structures by patterning trenches in the initial layer stack, forming an anchoring structure extending across the fin structures, and while the channel layers are anchored by the anchoring structure: removing the sacrificial layers by a selective etching of the first semiconductor material, thereby forming a longitudinal cavity underneath the channel layer of each fin structure, and depositing an insulating material to fill the cavities, wherein the insulating material is formed of a flowable dielectric, and subsequently recessing the at least one anchoring structure and the insulating material to a level below the cavities such that the insulating material remains in the cavities to form insulating layers underneath the channel layers of each fin structure.

公开(公告)号：US10903335B2

公开(公告)日：2021-01-26

申请号：US16408971

申请日：2019-05-10

Applicant: IMEC VZW

Inventor： Gaspard Hiblot ,  Sylvain Baudot ,  Hans Mertens ,  Julien Jussot

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/40 ,  H01L29/78 ,  H01L29/423

Abstract: A method of forming aligned gates for horizontal nanowires or nanosheets, comprising: providing a wafer which comprises at least one fin of sacrificial layers alternated with functional layers, and a dummy gate covering a section of the fin between a first end and a second end; at least partly removing the sacrificial layers at the first end and the second end thereby forming a void between the functional layers at the first and end such that the void is partly covered by the dummy gate; providing resist material which oxidizes upon EUV exposure; exposing the wafer to EUV light; selectively removing the dummy gate and the unexposed resist; forming a gate between the functional layers and between the exposed resist at the first end and at the second end.

公开(公告)号：US10468483B2

公开(公告)日：2019-11-05

申请号：US15822478

申请日：2017-11-27

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Hans Mertens

IPC: H01L29/06 ,  H01L21/306 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02

Abstract: The present disclosure relates to a method of forming a semiconductor device comprising horizontal nanowires. The method comprises depositing a multilayer stack on a substrate, the multilayer stack comprising first sacrificial layers alternated with layers of nanowire material; forming at least one fin in the multilayer stack; applying an additional sacrificial layer around the fin such that a resulting sacrificial layer is formed all around the nanowire material; and forming a nanowire spacer, starting from the resulting sacrificial layer, around the nanowire material at an extremity of the nanowire material. The present disclosure also relates to a corresponding semiconductor device.

公开(公告)号：US20180166535A1

公开(公告)日：2018-06-14

申请号：US15822478

申请日：2017-11-27

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Hans Mertens

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L21/306 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/30604 ,  H01L21/30612 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66439 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78651 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: The present disclosure relates to a method of forming a semiconductor device comprising horizontal nanowires. The method comprises depositing a multilayer stack on a substrate, the multilayer stack comprising first sacrificial layers alternated with layers of nanowire material; forming at least one fin in the multilayer stack; applying an additional sacrificial layer around the fin such that a resulting sacrificial layer is formed all around the nanowire material; and forming a nanowire spacer, starting from the resulting sacrificial layer, around the nanowire material at an extremity of the nanowire material. The present disclosure also relates to a corresponding semiconductor device.

公开(公告)号：US20240234207A9

公开(公告)日：2024-07-11

申请号：US18486370

申请日：2023-10-13

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Hans Mertens ,  Zsolt Tokei ,  Naoto Horiguchi

IPC: H01L21/768 ,  H01L23/528 ,  H01L29/40

CPC classification number: H01L21/76879 ,  H01L21/76802 ,  H01L23/5286 ,  H01L29/401

Abstract: A method provided for interconnecting a buried wiring line and a source/drain body. The method includes: forming a fin structure on a substrate, the fin structure comprising at least one channel layer; forming a buried wiring line in a trench extending alongside the fin structure, wherein the buried wiring line is capped by a first insulating layer structure; forming a source/drain body on the at least one channel layer by epitaxy; forming a via hole in the first insulating layer structure to expose an upper surface of the buried wiring line; forming a metal via in the via hole; forming a second insulating layer structure over the first insulating layer structure, wherein a contact opening is defined in the second insulating layer structure to expose the source/drain body and an upper via portion of the metal via; and forming a source/drain contact in the contact opening, on the upper via portion and the source/drain body, thereby inter-connecting the buried wiring line and the source/drain body.

公开(公告)号：US20240203994A1

公开(公告)日：2024-06-20

申请号：US18543815

申请日：2023-12-18

Applicant: IMEC VZW

Inventor： Anshul Gupta ,  Hans Mertens

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/768 ,  H01L23/50

CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/76805 ,  H01L23/50 ,  H01L29/66545

Abstract: The disclosure relates to a method for forming an integrated circuit device that includes forming a forksheet device on a frontside of a substrate, the forksheet device comprising a first and a second transistor separated by a vertically oriented dielectric wall, such that the forksheet device is formed over a base portion of the substrate and the dielectric wall extends into the base portion; subsequent to forming the forksheet device, thinning the substrate from a backside of the substrate; subsequent to the thinning, forming a first trench underneath the first transistor and a second trench underneath the second transistor by etching the base portion from the backside, the first and second trenches being separated by the dielectric wall; and forming a first backside wiring line in the first trench and a second backside wiring line in the second trench.

公开(公告)号：US20230197831A1

公开(公告)日：2023-06-22

申请号：US18063991

申请日：2022-12-09

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Hans Mertens ,  Eugenio Dentoni Litta

IPC: H01L29/66

CPC classification number: H01L29/66553 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/42392

Abstract: A method is provided for forming a semiconductor device. The method includes: forming a device layer stack on a substrate, the device layer stack comprising a bottom sacrificial layer and an alternating sequence of upper sacrificial layers and channel layers; forming a sacrificial gate structure; etching through at least the upper sacrificial and channel layers of the device layer stack while using the sacrificial gate structure as an etch mask; forming a sacrificial spacer covering end surfaces of the upper sacrificial and channel layers; while the sacrificial spacer masks the end surfaces of the upper sacrificial and channel layers, further etching the device layer stack to remove the bottom sacrificial layer and thereby form a cavity in the device layer stack; forming a dielectric layer in the cavity, wherein forming the dielectric layer comprises depositing and then etching back a dielectric bottom material to a level below a bottom-most one of the channel layers; removing the sacrificial spacer; forming recesses and forming inner spacers in the recesses; and forming source and drain regions by epitaxially growing semiconductor material on the end surfaces of the channel layers.