公开(公告)号：US20200090743A1

公开(公告)日：2020-03-19

申请号：US16593868

申请日：2019-10-04

Applicant: Intel Corporation

Inventor： Aliasgar S. MADRASWALA ,  Bharat M. PATHAK ,  Binh N. NGO ,  Naveen VITTAL PRABHU ,  Karthikeyan RAMAMURTHI ,  Pranav KALAVADE

IPC: G11C11/56 ,  G11C8/08 ,  G11C16/26 ,  G11C16/08

Abstract: A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.

公开(公告)号：US20200027503A1

公开(公告)日：2020-01-23

申请号：US16586214

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Lei CHEN ,  Yogesh B. WAKCHAURE ,  Aliasgar S. MADRASWALA ,  Xin GUO ,  Cole UHLMAN

IPC: G11C11/56 ,  G06F3/06 ,  G11C16/08

Abstract: A method and apparatus to reduce read retry operations in a NAND Flash memory is provided. To reduce the number of read retries for future reads, a word line group is assigned an optimal read voltage, the reference voltage that results in eliminating the read error for the word line is selected as the optimal read voltage (also referred to as a “sticky voltage”) for the word line group to be used for a next read of the page. An optimal read voltage per word line group for the page per NAND Flash memory die is stored in the lookup table. Storing an optimal read voltage per word line group instead of per die reduces the number of read retries.

公开(公告)号：US20190163403A1

公开(公告)日：2019-05-30

申请号：US16264390

申请日：2019-01-31

Applicant: Intel Corporation

Inventor： Aliasgar S. MADRASWALA ,  Naveen Vittal PRABHU

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40

Abstract: A method performed by a non volatile memory is described. The method includes receiving a first command from a controller to perform an operation. The method also includes receiving a second command from the controller to perform a read operation, where, the controller does not send a third command to suspend the operation between the first and second commands.

公开(公告)号：US20190102296A1

公开(公告)日：2019-04-04

申请号：US15721237

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Shankar NATARAJAN ,  Aliasgar S. MADRASWALA ,  Wayne D. TRAN

IPC: G06F12/0804 ,  G06F3/06

Abstract: In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the memory. Write data is preserved in the event of cached writes by data preservation logic in registers and data recovery logic recovers the preserved data and outputs the recovered data from the storage drive. Other aspects are described herein.

公开(公告)号：US20200250028A1

公开(公告)日：2020-08-06

申请号：US16267323

申请日：2019-02-04

Applicant: Intel Corporation

Inventor： Naveen Prabhu VITTAL PRABHU ,  Bharat M. PATHAK ,  Aliasgar S. MADRASWALA ,  Yogesh B. WAKCHAURE ,  Violante MOSCHIANO ,  Walter DI FRANCESCO ,  Michele INCARNATI ,  Antonino Giuseppe LA SPINA

IPC: G06F11/10 ,  G11C29/44 ,  G11C29/52 ,  G11C16/10 ,  G11C11/56 ,  G06F11/07

Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.

公开(公告)号：US20190227749A1

公开(公告)日：2019-07-25

申请号：US16367638

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Yogesh B. WAKCHAURE ,  Aliasgar S. MADRASWALA ,  David J. PELSTER ,  Donia SEBASTIAN ,  Curtis GITTENS ,  Xin GUO ,  Neelesh VEMULA ,  Varsha REGULAPATI ,  Naga Kiranmayee UPADHYAYULA

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26

Abstract: Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.

公开(公告)号：US20190034330A1

公开(公告)日：2019-01-31

申请号：US15829764

申请日：2017-12-01

Applicant: Intel Corporation

Inventor： Shankar NATARAJAN ,  Aliasgar S. MADRASWALA ,  Kristopher H. GAEWSKY ,  Jason CULP

IPC: G06F12/02 ,  G11C16/34 ,  G11C16/16 ,  G11C16/30

Abstract: An apparatus is described. The apparatus includes a mass storage device having a plurality of storage cells capable of storing more than one bit per cell. The plurality of storage cells are partitionable into a static single level (SLC) buffer, a dynamic SLC buffer and a primary multi-bit storage region. The mass storage device includes charge pump circuitry to program and erase the storage cells such that: a) those of the cells associated with the SLC buffer are to maintain larger stored charge potentials than those of the cells associated with the dynamic SLC buffer; and, b) those of the cells associated with the dynamic SLC buffer, when in SLC mode, are to receive fewer charge pump cycles during a program and/or erase sequence than those of the cells associated with the primary multi-bit storage region.

公开(公告)号：US20180004410A1

公开(公告)日：2018-01-04

申请号：US15197617

申请日：2016-06-29

Applicant: INTEL CORPORATION

Inventor： Aliasgar S. MADRASWALA ,  Yogesh B. WAKCHAURE ,  David B. CARLTON ,  Xin GUO ,  Ryan J. NORTON

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688

Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.