公开(公告)号：US11462536B2

公开(公告)日：2022-10-04

申请号：US16147538

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Anupama Bowonder ,  Rishabh Mehandru ,  Mark Bohr ,  Tahir Ghani

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Integrated circuit structures having asymmetric source and drain structures, and methods of fabricating integrated circuit structures having asymmetric source and drain structures, are described. For example, an integrated circuit structure includes a fin, and a gate stack over the fin. A first epitaxial source or drain structure is in a first trench in the fin at a first side of the gate stack. A second epitaxial source or drain structure is in a second trench in the fin at a second side of the gate stack, the second epitaxial source or drain structure deeper into the fin than the first epitaxial source or drain structure.

公开(公告)号：US11069795B2

公开(公告)日：2021-07-20

申请号：US16636206

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： Karthik Jambunathan ,  Glenn A. Glass ,  Anand S. Murthy ,  Jun Sung Kang ,  Bruce E. Beattie ,  Anupama Bowonder ,  Biswajeet Guha ,  Ju H. Nam ,  Tahir Ghani

IPC: H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: Integrated circuits include fins including an upper/channel region and a lower/sub-channel region, the lower region having a first chemical composition and opposing sidewalls adjacent to an insulator material, and the upper region having a second chemical composition. A first width indicates the distance between the opposing sidewalls of the lower region at a first location is at least 1 nm wider than a second width indicating the distance between the opposing sidewalls of the upper region at a second location, the first location being within 10 nm of the second location (or otherwise relatively close to one another). The first chemical composition is distinct from the second chemical composition and includes a surface chemical composition at an outer surface of the opposing sidewalls of the lower region and a bulk chemical composition therebetween, the surface chemical composition including one or more of oxygen, nitrogen, carbon, chlorine, fluorine, and sulfur.

公开(公告)号：US20240213100A1

公开(公告)日：2024-06-27

申请号：US18087879

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Swapnadip Ghosh ,  Yulia Gotlib ,  Chiao-ti Huang ,  Bishwajit Debnath ,  Anupama Bowonder ,  Matthew J. Prince

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823878 ,  H01L21/28123 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L24/16 ,  H01L2224/16225

Abstract: Techniques are provided herein to form semiconductor devices that include one or more gate cuts having a hybrid material structure. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that includes a hybrid structure having both a low-k dielectric material and a high-k dielectric material. The gate cut includes an outer layer having a high-k dielectric material and a dielectric fill on the dielectric layer having a low-k dielectric material. The inclusion of low-k dielectric material reduces the parasitic capacitance between adjacent conductive layers around or within the gate cut.

公开(公告)号：US12021149B2

公开(公告)日：2024-06-25

申请号：US18143549

申请日：2023-05-04

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand S. Murthy ,  Tahir Ghani ,  Anupama Bowonder

IPC: H01L21/00 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7853 ,  H01L29/165 ,  H01L29/66818 ,  H01L29/7851

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US11984449B2

公开(公告)日：2024-05-14

申请号：US17968558

申请日：2022-10-18

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Stephen Cea ,  Biswajeet Guha ,  Anupama Bowonder ,  Tahir Ghani

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/267 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/267

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

公开(公告)号：US11901457B2

公开(公告)日：2024-02-13

申请号：US16700431

申请日：2019-12-02

Applicant: Intel Corporation

Inventor： Szuya S. Liao ,  Rahul Pandey ,  Rishabh Mehandru ,  Anupama Bowonder ,  Pratik Patel

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66795

Abstract: Fin shaping, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure above a substrate. The protruding fin portion has substantially vertical upper sidewalls and outwardly tapered lower sidewalls. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region is at a first side of the gate stack, and a second source or drain region is at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US11600696B2

公开(公告)日：2023-03-07

申请号：US16457347

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Rishabh Mehandru ,  Stephen Cea ,  Anupama Bowonder ,  Juhyung Nam ,  Willy Rachmady

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.

公开(公告)号：US11430868B2

公开(公告)日：2022-08-30

申请号：US16020361

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Biswajeet Guha ,  Anupama Bowonder ,  Anand S. Murthy ,  Tahir Ghani ,  Stephen M. Cea

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/74 ,  H01L29/66 ,  H01L29/20 ,  H01L29/161 ,  H01L29/16

Abstract: Integrated circuit structures including a buried etch-stop layer to help control transistor source/drain depth are provided herein. The buried etch-stop layer addresses the issue of the source/drain etch (or epi-undercut (EUC) etch) going below the bottom of the active height of the channel region, as such an issue can result in un-controlled sub-fin leakage that causes power consumption degradation and other undesired performance issues. The buried etch-stop layer is formed below the channel material, such as in the epitaxial stack that includes the channel material, and acts to slow the removal of material after the channel material has been removed when etching to form the source/drain trenches. In other words, the buried etch-stop layer includes different material from the channel material that can be etched, for at least one given etchant, at a relatively slower rate than the channel material to help control the source/drain trench depth.

公开(公告)号：US20200220014A1

公开(公告)日：2020-07-09

申请号：US16640465

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Karthik Jambunathan ,  Biswajeet Guha ,  Anupama Bowonder ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/78 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8234

Abstract: Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

公开(公告)号：US20240222447A1

公开(公告)日：2024-07-04

申请号：US18090048

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Reken Patel ,  Conor P. Puls ,  Krishna Ganesan ,  Akitomo Matsubayashi ,  Diana Ivonne Paredes ,  Sunzida Ferdous ,  Brian Greene ,  Lateef Uddin Syed ,  Kyle T. Horak ,  Lin Hu ,  Anupama Bowonder ,  Swapnadip Ghosh ,  Amritesh Rai ,  Shruti Subramanian ,  Gordon S. Freeman

IPC: H01L29/417 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/28123 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: An integrated circuit includes a first device, and a laterally adjacent second device. The first device includes a first body of semiconductor material extending laterally from a first source or drain region, a first gate structure on the first body, and a first contact extending vertically upward from the first source or drain region. The second device includes a second body of semiconductor material extending laterally from a second source or drain region, a second gate structure on the second body, and a second contact extending vertically upward from the second source or drain region. A gate cut structure including dielectric material is laterally between the first gate structure and the second gate structure, and also laterally between the first contact and the second contact. In some examples, a third contact extends laterally from the first contact to the second contact and passes over the gate cut structure.