公开(公告)号：US20180374951A1

公开(公告)日：2018-12-27

申请号：US15777707

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  JACOB M. JENSEN ,  DANIEL B. AUBERTINE ,  CHANDRA S. MOHAPATRA

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Tensile strain is applied to a channel region of a transistor by depositing an amorphous SixGe1-x-yCy alloy in at least one of a source and a drain (S/D) region of the transistors. The amorphous SixGe1-x-yCy alloy is crystallized, thus reducing the unit volume of the alloy. This volume reduction in at least one of the source and the drain region applies strain to a connected channel region. This strain improves electron mobility in the channel. Dopant activation in the source and drain locations is recovered during conversion from amorphous to crystalline structure. Presence of high carbon concentrations reduces dopant diffusion from the source and drain locations into the channel region. The techniques may be employed with respect to both planar and non-planar (e.g., FinFET and nanowire) transistors.

公开(公告)号：US20180337235A1

公开(公告)日：2018-11-22

申请号：US15776996

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： WILLY RACHMADY ,  MATTHEW V. METZ ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  NADIA M. RAHHAL-ORABI ,  Jack T. KAVALIEROS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L29/10 ,  H01L29/205 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: Embodiments of the present disclosure describe a semiconductor multi-gate transistor having a semi-conductor fin extending from a substrate and including a sub-fin region and an active region. The subfin region may include a dielectric material region under the gate to provide improved isolation. The dielectric material region may be formed during a replacement gate process by replacing a portion of a sub-fin region under the gate with the dielectric material region, followed by fabrication of a replacement gate structure. The sub-fin region may be comprised of group III-V semiconductor materials in various combinations and concentrations. The active region may be comprised of a different group III-V semiconductor material. The dielectric material region may be comprised of amorphous silicon. Other embodiments may be described and/or claimed.

公开(公告)号：US20180331184A1

公开(公告)日：2018-11-15

申请号：US15777553

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  KARTHIK JAMBUNATHAN ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  SEIYON KIM ,  JUN SUNG KANG

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/78 ,  H01L21/764 ,  H01L29/66

CPC classification number: H01L29/1083 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: Techniques are disclosed for fabricating semiconductor transistor devices configured with a sub-fin insulation layer that reduces parasitic leakage (i.e., current leakage through a portion of an underlying substrate between a source region and a drain region associated with a transistor). The parasitic leakage is reduced by fabricating transistors with a sacrificial layer in a sub-fin region of the substrate below at least a channel region of the fin. During processing, the sacrificial layer in the sub-fin region is removed and replaced, either in whole or in part, with a dielectric material. The dielectric material increases the electrical resistivity of the substrate between corresponding source and drain portions of the fin, thus reducing parasitic leakage.

公开(公告)号：US20180323310A1

公开(公告)日：2018-11-08

申请号：US15529432

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： HAROLD W. KENNEL ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  TAHIR GHANI

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/78 ,  H01L29/778 ,  H01L27/06

CPC classification number: H01L29/78681 ,  H01L27/0605 ,  H01L29/1054 ,  H01L29/7783 ,  H01L29/78 ,  H01L29/785

Abstract: Semiconductor devices including a subfin including a first III-V semiconductor alloy and a channel including a second III-V semiconductor alloy are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V semiconductor alloy is deposited on the substrate within the trench and the second III-V semiconductor alloy is epitaxially grown on the first III-V semiconductor alloy. In some embodiments, a conduction band offset between the first III-V semiconductor alloy and the second III-V semiconductor alloy is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.

公开(公告)号：US20170358645A1

公开(公告)日：2017-12-14

申请号：US15525269

申请日：2014-12-26

Applicant: INTEL CORPORATION

Inventor： GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  TAHIR GHANI ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  SANAZ K. GARDNER ,  MARKO RADOSAVLJEVIC ,  GLENN A. GLASS

IPC: H01L29/06 ,  H01L29/12 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L29/775 ,  H01L21/306 ,  H01L21/02 ,  H01L29/20 ,  H01L29/161 ,  H01L29/04

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/7605 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/122 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.

公开(公告)号：US20170345900A1

公开(公告)日：2017-11-30

申请号：US15527221

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： HAROLD W. KENNEL ,  MATTHEW V. METZ ,  WILLY RACHMADY ,  GILBERT DEWEY ,  CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  TAHIR GHANI

IPC: H01L29/205 ,  H01L21/02 ,  H01L21/18

CPC classification number: H01L29/205 ,  H01L21/02455 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/182 ,  H01L21/185

Abstract: Semiconductor devices including a subfin including a first III-V compound semiconductor and a channel including a second III-V compound semiconductor are described. In some embodiments the semiconductor devices include a substrate including a trench defined by at least two trench sidewalls, wherein the first III-V compound semiconductor is deposited on the substrate within the trench and the second III-V compound semiconductor is epitaxially grown on the first III-V compound semiconductor. In some embodiments, a conduction band offset between the first III-V compound semiconductor and the second III-V compound semiconductor is greater than or equal to about 0.3 electron volts. Methods of making such semiconductor devices and computing devices including such semiconductor devices are also described.

公开(公告)号：US20170323962A1

公开(公告)日：2017-11-09

申请号：US15525164

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： GILBERT DEWEY ,  MATTHEW V. METZ ,  JACK T. KAVALIEROS ,  WILLY RACHMADY ,  TAHIR GHANI ,  ANAND S. MURTHY ,  CHANDRA S. MOHAPATRA ,  HAROLD W. KENNEL ,  GLENN A. GLASS

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7781

Abstract: An embodiment includes a device comprising: a trench that includes a doped trench material having: (a)(i) a first bulk lattice constant and (a)(ii) at least one of a group III-V material and a group IV material; a fin structure, directly over the trench, including fin material having: (b) (ii) a second bulk lattice constant and (b)(ii) at least one of a group III-V material and a group IV material; a barrier layer, within the trench and directly contacting a bottom surface of the fin, including a barrier layer material having a third bulk lattice constant; wherein (a) the trench has an aspect ratio (depth to width) of at least 1.5:1, and (b) the barrier layer has a height not greater than a critical thickness for the barrier layer material. Other embodiments are described herein.