公开(公告)号：US20190272936A1

公开(公告)日：2019-09-05

申请号：US15911549

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Cheng XU ,  Ying WANG ,  Junnan ZHAO ,  Meizi JIAO ,  Yikang DENG

IPC: H01F27/24 ,  G05F1/10 ,  H01L49/02 ,  H01F41/02

Abstract: Embodiments include inductors with embedded magnetic cores and methods of forming such inductors. Some embodiments may include an integrated circuit package that utilizes such inductors. For example, the integrated circuit package may include an integrated circuit die and a multi-phase voltage regulator electrically coupled to the integrated circuit die. In an embodiment, the multi-phase voltage regulator includes a substrate core and a plurality of inductors in the substrate core. In an embodiment, the inductors may include a conductive loop in and around the substrate core. In an embodiment, the conductive loops are electrically coupled to a voltage out line. Embodiments may also include a magnetic core surrounded by the conductive loops. The magnetic core is separated from surfaces of the conductive loops by the substrate core

公开(公告)号：US20240405006A1

公开(公告)日：2024-12-05

申请号：US18805232

申请日：2024-08-14

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Cheng XU ,  Junnan ZHAO ,  Ying WANG ,  Meizi JIAO

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/498 ,  H01L23/528 ,  H01L23/538

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

公开(公告)号：US20230369192A1

公开(公告)日：2023-11-16

申请号：US18226652

申请日：2023-07-26

Applicant: Intel Corporation

Inventor： Jonathan ROSCH ,  Wei-Lun JEN ,  Cheng XU ,  Liwei CHENG ,  Andrew BROWN ,  Yikang DENG

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49827 ,  H05K1/111 ,  H01L21/486 ,  H05K1/115 ,  H01L23/49822 ,  H05K2201/09727 ,  H05K1/025 ,  H05K2201/09736 ,  H05K2201/09827 ,  H05K1/18 ,  H05K2201/095

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

公开(公告)号：US20220117089A1

公开(公告)日：2022-04-14

申请号：US17560004

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Ying WANG ,  Junnan ZHAO ,  Cheng XU ,  Yikang DENG

IPC: H05K1/16 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H01F41/04 ,  H01F27/28 ,  H01F17/00

Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.

公开(公告)号：US20200266149A1

公开(公告)日：2020-08-20

申请号：US16646932

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Cheng XU ,  Junnan ZHAO ,  Ji Yong PARK ,  Kyu Oh LEE

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

Abstract: Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.

公开(公告)号：US20200006180A1

公开(公告)日：2020-01-02

申请号：US16024697

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Andrew BROWN ,  Ji Yong PARK ,  Siddharth ALUR ,  Cheng XU ,  Amruthavalli ALUR

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/29

Abstract: Embodiments include an electronic package and methods of forming an electronic package. In an embodiment, the electronic package comprises a substrate, and a plurality of conductive features formed over the substrate. In an embodiment, a bilayer build-up layer is formed over the plurality of conductive features. In an embodiment, the bilayer build-up layer comprises a first dielectric layer and a second dielectric layer. In an embodiment, a surface of the first dielectric layer comprises depressions. In an embodiment, the second dielectric layer is disposed in the depressions of the surface of the first dielectric layer.

公开(公告)号：US20190355675A1

公开(公告)日：2019-11-21

申请号：US15982652

申请日：2018-05-17

Applicant: Intel Corporation

Inventor： Kyu-Oh LEE ,  Sai VADLAMANI ,  Rahul JAIN ,  Junnan ZHAO ,  Ji Yong PARK ,  Cheng XU ,  Seo Young KIM

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01F1/12 ,  H01F41/14

Abstract: Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.