公开(公告)号：US20180375438A1

公开(公告)日：2018-12-27

申请号：US15631996

申请日：2017-06-23

Applicant: Intel Corporation

Inventor： Sameer Shekhar ,  Amit K. Jain ,  Alexander Waizman ,  Michael Zelikson ,  Chin Lee Kuan

IPC: H02M3/335 ,  G05F1/46 ,  H02M1/36 ,  H02M3/24

Abstract: An apparatus is provided which comprises: a first voltage regulator; a second voltage regulator; and a switch to selectively couple the first voltage regulator to the second voltage regulator, such that a first output node of the first voltage regulator is temporarily coupled to a second output node of the second voltage regulator via the switch.

公开(公告)号：US20180364775A1

公开(公告)日：2018-12-20

申请号：US15627159

申请日：2017-06-19

Applicant: Intel Corporation

Inventor： Amit K. Jain ,  Chin Lee Kuan ,  Sameer Shekhar

IPC: G06F1/26

Abstract: Described is an apparatus which comprises: a power supply node; a plurality of inductors inductively coupled with one another, wherein at least one inductor of the plurality is electrically coupled to the power supply node; a plurality of loads; and a plurality of capacitors coupled to the plurality of inductors, respectively, and also coupled to the plurality of loads, respectively.

公开(公告)号：US12256487B2

公开(公告)日：2025-03-18

申请号：US17367674

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Seok Ling Lim ,  Chin Lee Kuan ,  Tin Poay Chuah

IPC: H05K1/02 ,  H05K3/46

Abstract: The present disclosure is directed to a hybrid dielectric interconnect stack for a printed circuit board having a first dielectric layer with a first dielectric constant and a first dielectric loss tangent positioned over an intermediate layer, which includes a first dielectric sublayer with a first sublayer dielectric constant and a first sublayer dielectric loss tangent, an embedded conductive layer, and a second dielectric sublayer with a second sublayer dielectric constant and a second sublayer dielectric loss tangent, in which the embedded conductive layer is positioned between the first and second dielectric sublayers, and a second dielectric layer with a second dielectric constant and a second dielectric loss tangent, in which the intermediate layer is positioned between the first and second dielectric layers.

公开(公告)号：US20230124098A1

公开(公告)日：2023-04-20

申请号：US17503413

申请日：2021-10-18

Applicant: Intel Corporation

Inventor： Chin Lee Kuan ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/498 ,  H01L21/48

Abstract: The present disclosure is directed to a semiconductor package including: a package substrate including a top surface, lateral sides and a bottom surface; a ball grid array including a plurality of solder balls coupled to the bottom surface; a stiffener including a bottom portion affixed to the bottom surface of the package substrate and a lateral portion extending from the bottom portion and affixed to the lateral sides of the package substrate, the bottom portion of the stiffener including a plurality of openings for the plurality of solder balls, wherein the top surface of the package substrate is substantially flush with a top surface of the lateral portion; and an electronic component coupled to the top surface of the package substrate.

公开(公告)号：US11521943B2

公开(公告)日：2022-12-06

申请号：US17229316

申请日：2021-04-13

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Tin Poay Chuah ,  Chin Lee Kuan

IPC: H05K1/18 ,  H01L23/64 ,  H01L23/498 ,  H05K1/02 ,  H01L23/50 ,  H01L23/13

Abstract: A capacitor loop substrate assembly includes a substrate with a loop shape, one or more capacitors or other electronic components on the substrate, and an opening in the substrate to allow the capacitor loop substrate assembly to be coupled to an integrated circuit package, such as a package including a die. Interconnects and/or contacts for interconnects are formed in an integrated circuit package to couple the capacitor loop substrate assembly to the integrated circuit package.

公开(公告)号：US20220375898A1

公开(公告)日：2022-11-24

申请号：US17323094

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Vishram Shriram Pandit ,  Narayanan Natarajan ,  Jayanth M. Kalyan ,  Khondker Z. Ahmed ,  Jonathan P. Douglas ,  Gururaj K. Shamanna ,  Chin Lee Kuan

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48

Abstract: An Integrated Circuit (IC) package is provided, comprising a first IC die having a first capacitor and a logic circuit, and a second IC die having a second capacitor. The first IC die and the second IC die may be stacked within the IC package one on top of another and electrically coupled with die-to-die interconnects. The logic circuit is electrically coupled in a power delivery network to the first capacitor and the second capacitor. The first IC die and the second IC die include respective back-end-of-line portions in which the first capacitor and the second capacitor, which may comprise metal-insulator-metal capacitors in some embodiments are situated. In some embodiments, the second capacitor is situated in a shadow of the logic circuit. In various embodiments, the first IC die and the second IC die comprise any suitable pair in a plurality of stacked IC dies within an IC package.

公开(公告)号：US11133256B2

公开(公告)日：2021-09-28

申请号：US16446920

申请日：2019-06-20

Applicant: Intel Corporation

Inventor： Amit Kumar Jain ,  Sameer Shekhar ,  Chin Lee Kuan ,  Kevin Joseph Doran ,  Dong-Ho Han

IPC: H01L23/538 ,  H01L49/02 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate; a bridge, embedded in the package substrate, wherein the bridge includes an integral passive component, and wherein a surface of the bridge include first contacts in a first interconnect area and second contacts in a second interconnect area; a first die coupled to the passive component via the first contacts in the first interconnect area; and a second die coupled to the second contacts in the second interconnect area.

公开(公告)号：US10985147B2

公开(公告)日：2021-04-20

申请号：US16017719

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Jenny Shio Yin Ong ,  Seok Ling Lim ,  Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Chin Lee Kuan

IPC: H01L25/16 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00 ,  H01L23/538 ,  H01L23/498

Abstract: A stiffener on a semiconductor package substrate includes a plurality of parts that are electrically coupled to the semiconductor package substrate on a die side. Both stiffener parts are electrically contacted through a passive device that is soldered between the two stiffener parts and by an electrically conductive adhesive that bonds a given stiffener part to the semiconductor package substrate. The passive device is embedded between two stiffener parts to create a smaller X-Y footprint as well as a lower Z-direction profile.

公开(公告)号：US10171033B2

公开(公告)日：2019-01-01

申请号：US15469499

申请日：2017-03-25

Applicant: INTEL CORPORATION

Inventor： Khang Choong Yong ,  Raymond Chong ,  Ramaswamy Parthasarathy ,  Stephen Hall ,  Chin Lee Kuan

IPC: H03B5/32 ,  H03L7/06

Abstract: An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end is coupled to the input; a second interconnect line having first and second ends, wherein the first end is coupled to the output; a first capacitor coupled to the input and ground; and a second capacitor coupled to the second end of the second interconnect line. An apparatus is provided which comprises: a high pass filter; a pair of AC coupling capacitors coupled to the high pass filter; a low pass filter coupled to the pair of AC coupling capacitors; and an analog to digital converter (ADC) coupled to the low pass filter.

公开(公告)号：US20170373587A1

公开(公告)日：2017-12-28

申请号：US15195671

申请日：2016-06-28

Applicant: Intel Corporation

Inventor： Chin Lee Kuan ,  Sameer Shekhar ,  Amit K. Jain

IPC: H02M1/14 ,  H05K1/18 ,  H05K1/02 ,  H02M1/00

CPC classification number: H02M1/14 ,  G06F1/26 ,  H02M2001/009 ,  H05K1/0231

Abstract: Methods and apparatus relating to a compact partitioned capacitor design for multiple voltage and/or load domains (e.g., with improved decoupling) are described. In an embodiment, a capacitor provides substrate decoupling for a plurality of loads. Moreover, the capacitor is capable of decoupling two or more voltage domains. Furthermore, in some embodiments the capacitor is capable of decoupling two or more voltage domains and mitigating self-noise and/or cross-noise between them. Other embodiments are also disclosed and claimed.