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    Multiple reticle field semiconductor devices
    11.
    发明授权
    Multiple reticle field semiconductor devices 有权

    公开(公告)号：US11043459B2

    公开(公告)日：2021-06-22

    申请号：US16611129

    申请日：2017-06-29

    Applicant: INTEL CORPORATION

    Inventor： Edward A. Burton ,  Mark T. Bohr ,  Murray Fitzpatrick Kelley ,  Shawn Michael Klauser

    IPC: H01L23/544 ,  H01L23/538 ,  G03F7/20

    Abstract: Techniques are described for fabricating integrated circuit devices that span multiple reticle fields. Integrated circuits formed within separate reticle fields are placed into electrical contact with each other by overlapping reticle fields to form an overlapping conductive interconnect. This overlapping conductive interconnect electrically connects an interconnect layer of a first reticle field with an interconnect layer of a second, laterally adjacent reticle field. The overlapping conductive interconnection extends into a common scribe zone between adjacent reticle fields.

    SEMICONDUCTOR DEVICE HAVING VOLTAGE REGULATORS EMBEDDED IN LAYERED PACKAGE
    12.
    发明申请
    SEMICONDUCTOR DEVICE HAVING VOLTAGE REGULATORS EMBEDDED IN LAYERED PACKAGE 审中-公开

    公开(公告)号：US20200219864A1

    公开(公告)日：2020-07-09

    申请号：US16820948

    申请日：2020-03-17

    Applicant: Intel Corporation

    Inventor： Edward A. Burton

    IPC: H01L25/18 ,  H01L23/538 ,  H01L23/31 ,  H01L25/00

    Abstract: A computing chip can include one or more voltage regulators to decrease a standard voltage, such as twelve volts, to a relatively low operating voltage of its processing cores, typically around one volt. Because the power consumed by the cores can be substantial, such as three hundred watts or more, it is desirable to locate the voltage regulators as close as possible to the cores, to reduce the distances that relatively large currents have to travel in the chip circuitry. The voltage regulators can be embedded within the package, such as in a layered structure, in a layer that electrically connects to the cores. While the cores are typically manufactured using the smallest possible lithographic features, the voltage regulators are less demanding and can instead use relatively large lithographic features, which can be formed using relatively old technology, and can therefore be relatively inexpensive.

    DIGITALLY COORDINATED DYNAMICALLY ADAPTABLE CLOCK AND VOLTAGE SUPPLY APPARATUS AND METHOD
    15.
    发明申请
    DIGITALLY COORDINATED DYNAMICALLY ADAPTABLE CLOCK AND VOLTAGE SUPPLY APPARATUS AND METHOD 有权

    公开(公告)号：US20210055921A1

    公开(公告)日：2021-02-25

    申请号：US16550134

    申请日：2019-08-23

    Applicant: Intel Corporation

    Inventor： Julien Sebot ,  Edward A. Burton ,  Nasser A. Kurd ,  Jonathan Douglas

    IPC: G06F8/41 ,  G06F9/30 ,  H03L7/08

    Abstract: An apparatus and method is described that digitally coordinates dynamically adaptable clock and voltage supply to significantly reduce the energy consumed by a processor without impacting its performance or latency. A signal is generated that indicates a long latency operation. This signal is used to reduce power supply voltage and frequency of the adaptable clock. An early resume indicator is generated a few nanoseconds before normal operations are about to resume. This early resume signal is used to power up the power-downed voltage regulator, and/or can increase frequency and/or supply voltage back to normal level before normal processor operations are about to resume.

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