公开(公告)号：US20220181335A1

公开(公告)日：2022-06-09

申请号：US17673670

申请日：2022-02-16

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Brian S. DOYLE ,  Ravi PILLARISETTY ,  Prashant MAJHI ,  Elijah V. KARPOV

IPC: H01L27/1159 ,  G11C11/22 ,  H01L29/51 ,  H01L29/78

Abstract: A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.

公开(公告)号：US20200243543A1

公开(公告)日：2020-07-30

申请号：US16635966

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Abhishek A. SHARMA ,  Prashant MAJHI ,  Elijah V. KARPOV ,  Brian S. DOYLE

IPC: H01L27/108 ,  G11C11/4096

Abstract: A memory device comprises a first selector and a storage capacitor in series with the first selector. A second selector is in parallel with the storage capacitor coupled between the first selector and zero volts. A plurality of memory devices form a 2S-1C cross-point DRAM array with 4F2 or less density.

公开(公告)号：US20230099724A1

公开(公告)日：2023-03-30

申请号：US17485312

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Elijah V. KARPOV ,  Sou-Chi CHANG ,  Uygar E. AVCI ,  Shriram SHIVARAMAN

IPC: H01L27/11507

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, to memory devices having ferroelectric capacitors coupled between intersecting bitlines and wordlines. Other embodiments may be disclosed or claimed.

公开(公告)号：US20220130443A1

公开(公告)日：2022-04-28

申请号：US17570249

申请日：2022-01-06

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Brian S. DOYLE ,  Ravi PILLARISETTY ,  Prashant MAJHI ,  Elijah V. KARPOV

IPC: G11C11/22 ,  H01L27/11585

Abstract: A 1S-1T ferroelectric memory cell is provided that include a transistor and a two-terminal selector device. The transistor exhibits a low conductive state and a high conductive state (channel resistance), depending on drive voltage. The two-terminal selector device exhibits one of an ON-state and an OFF-state depending upon whether the transistor is in its low conductive state or its high conductive state. The transistor may be, for instance, a ferroelectric gate vertical transistor. Modulation of a polarization state of ferroelectric material of the vertical transistor may be utilized to switch the state of the selector device. The memory cell may thus selectively be operated in one of an ON-state and an OFF-state depending upon whether the selector device is in its ON-state or OFF-state.

公开(公告)号：US20200321395A1

公开(公告)日：2020-10-08

申请号：US16635948

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Brian S. DOYLE ,  Abhishek A. SHARMA ,  Ravi PILLARISETTY ,  Elijah V. KARPOV ,  Prashant MAJHI

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/12 ,  H01L45/00

Abstract: Embedded non-volatile memory structures having an independently sized selector element and memory element are described. In an example, a memory device includes a metal layer. A selector element is above the metal layer. A memory element is above the metal line. A spacer surrounds one of the selector element and the memory element having a smallest width, and wherein the one of the selector element and the memory element not surrounded by the spacer has a width substantially identical to the spacer and is in alignment with the spacer.

公开(公告)号：US20200212075A1

公开(公告)日：2020-07-02

申请号：US16633559

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Brian S. DOYLE ,  Abhishek A. SHARMA ,  Ravi PILLARISETTY ,  Prashant MAJHI ,  Elijah V. KARPOV

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/417 ,  H01L21/768 ,  H01L21/027 ,  H01L29/786 ,  H01L29/66

Abstract: Thin film transistors having relatively increased width and shared bitlines are described. In an example, an integrated circuit structure includes a plurality of transistors formed in an insulator structure above a substrate. The plurality of transistors arranged in a column such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width. A first conductive contact is formed between one of sources and drains of at least two of the plurality of transistors in the column, and the conductive contact extends through the insulator structure at least two interconnect levels.

公开(公告)号：US20200168274A1

公开(公告)日：2020-05-28

申请号：US16636904

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Ravi PILLARISETTY ,  Abhishek A. SHARMA ,  Brian S. DOYLE ,  Elijah V. KARPOV ,  Prashant MAJHI

IPC: G11C13/00 ,  H01L27/24

Abstract: One embodiment of a memory device comprises a selector and a storage capacitor in series with the selector. A further embodiment comprises a conductive bridging RAM (CBRAM) in parallel with a storage capacitor coupled between the selector and zero volts. A plurality of memory devices form a 1S-1C or a 1S-1C-CBRAM cross-point DRAM array with 4F2 or less density.

公开(公告)号：US20180165065A1

公开(公告)日：2018-06-14

申请号：US15575334

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Charles C. KUO ,  Justin S. BROCKMAN ,  Juan G. ALZATE VINASCO ,  Kaan OGUZ ,  Kevin P. O'BRIEN ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Satyarth SURI ,  Robert S. CHAU ,  Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV

IPC: G06F7/58 ,  H01L43/08 ,  H01L43/02

CPC classification number: G06F7/588 ,  H01L43/02 ,  H01L43/08

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.

公开(公告)号：US20160365385A1

公开(公告)日：2016-12-15

申请号：US15247710

申请日：2016-08-25

Applicant: INTEL CORPORATION

Inventor： Ravi PILLARISETTY ,  Brian S. DOYLE ,  Elijah V. KARPOV ,  David L. KENCKE ,  Uday SHAH ,  Charles C. KUO ,  Robert S. CHAU

IPC: H01L27/24 ,  H01L29/78 ,  H01L45/00 ,  H01L29/66

CPC classification number: H01L27/2436 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L2029/7858

Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

公开(公告)号：US20200235162A1

公开(公告)日：2020-07-23

申请号：US16632065

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV ,  Brian S. DOYLE ,  Abhishek A. SHARMA

IPC: H01L27/24 ,  H01L27/22 ,  H01L45/00

Abstract: Embedded non-volatile memory structures having double selector elements are described. In an example, a memory device includes a word line. A double selector element is above the word line. The double selector element includes a first selector material layer, a second selector material layer different than the first selector material layer, and a conductive layer directly between the first selector material layer and the second selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the double selector element and the bipolar memory element. A bit line is above the word line.