公开(公告)号：US20190295943A1

公开(公告)日：2019-09-26

申请号：US16316528

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Elliot N. TAN

IPC: H01L23/522 ,  H01L21/768

Abstract: A first metallization layer is deposited on a first insulating layer on a substrate. The first metallization layer comprises a set of first conductive lines. A second metallization layer is deposited over the first metallization layer. The second metallization layer comprises a set of second conductive lines that cross the set of first conductive lines to form intersection regions. At least one of the intersection regions comprises a first portion of one of the first conductive lines and a second portion of one of the second conductive lines that crosses the first portion. A plurality of preformed connections are disposed between the first metallization layer and the second metallization layer at the plurality of intersection region. At least one of the preformed connections comprises a second insulating layer aligned to the second portion and the first portion.

公开(公告)号：US20180204763A1

公开(公告)日：2018-07-19

申请号：US15743616

申请日：2015-09-10

Applicant: WALLACE H. Charles ,  SIVAKUMAR Swaminathan ,  Intel Corporation

Inventor： Charles H. WALLACE ,  Elliot N. TAN ,  Paul A. NYHUS ,  Swaminathan SIVAKUMAR

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528

Abstract: Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.

公开(公告)号：US20240071917A1

公开(公告)日：2024-02-29

申请号：US18384582

申请日：2023-10-27

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0886 ,  H01L29/7848

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20220199807A1

公开(公告)日：2022-06-23

申请号：US17129867

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Sarah ATANASOV ,  Abhishek A. Sharma ,  Bernhard SELL ,  Chieh-Jen KU ,  Elliot N. TAN ,  Hui Jae YOO ,  Travis W. LAJOIE ,  Van H. LE ,  Pei-Hua WANG ,  Jason PECK ,  Tobias BROWN-HEFT

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8234

Abstract: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed

公开(公告)号：US20200066629A1

公开(公告)日：2020-02-27

申请号：US16346873

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L27/088 ,  H01L23/532 ,  H01L29/78 ,  H01L23/522

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20200066521A1

公开(公告)日：2020-02-27

申请号：US16489331

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Kevin LIN ,  Rami HOURANI ,  Elliot N. TAN ,  Manish CHANDHOK ,  Anant H. JAHAGIRDAR ,  Robert L. BRISTOL ,  Richard E. SCHENKER ,  Aaron Douglas LILAK

IPC: H01L21/033 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3115

Abstract: A computing device including tight pitch features and a method of fabricating a computing device using colored spacer formation is disclosed. The computing device includes a memory and an integrated circuit coupled to the memory. The integrated circuit includes a first multitude of features above a substrate. The integrated circuit die includes a second multitude of features above the substrate. The first multitude of features and the second multitude of features are same features disposed in a first direction. The first multitude of features interleave with the second multitude of features. The first multitude of features has a first size and the second multitude of features has a second size.

公开(公告)号：US20190148220A1

公开(公告)日：2019-05-16

申请号：US16246373

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Charles H. WALLACE ,  Elliot N. TAN ,  Paul A. NYHUS ,  Swaminathan SIVAKUMAR

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528

Abstract: Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.

公开(公告)号：US20180033692A1

公开(公告)日：2018-02-01

申请号：US15730647

申请日：2017-10-11

Applicant: Intel Corporation

Inventor： Charles H. WALLACE ,  Paul A. NYHUS ,  Elliot N. TAN ,  Swaminathan SIVAKUMAR

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76883 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line composed of alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.