公开(公告)号：US20220130719A1

公开(公告)日：2022-04-28

申请号：US17568648

申请日：2022-01-04

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Robert L. BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI ,  Marie KRYSAK

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US20210225698A1

公开(公告)日：2021-07-22

申请号：US17218080

申请日：2021-03-30

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Richard E. SCHENKER ,  Jeffery D. BIELEFELD ,  Rami HOURANI ,  Manish CHANDHOK

IPC: H01L21/768 ,  H01L23/528

Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.

公开(公告)号：US20160190060A1

公开(公告)日：2016-06-30

申请号：US14909736

申请日：2013-09-27

Applicant: Rami HOURANI ,  INTEL CORPORATION

Inventor： Robert L. Bristol ,  James M. BLACKWELL ,  Scott B. CLENDENNING ,  Florian GSTREIN ,  Eungnak HAN ,  Grant M. KLOSTER ,  Jeanette M. ROBERTS ,  Patricio E. ROMERO ,  Rami HOURANI

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3205 ,  H01L23/522 ,  H01L21/3105

CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/32 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

Abstract translation: 一个方面的方法包括通过通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。 该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。 在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。

公开(公告)号：US20210091194A1

公开(公告)日：2021-03-25

申请号：US16579069

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Rami HOURANI ,  Richard VREELAND ,  Giselle ELBAZ ,  Manish CHANDHOK ,  Richard E. SCHENKER ,  Gurpreet SINGH ,  Florian GSTREIN ,  Nafees KABIR ,  Tristan A. TRONIC ,  Eungnak HAN

IPC: H01L29/423 ,  H01L29/78 ,  H01L23/522 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

公开(公告)号：US20210091075A1

公开(公告)日：2021-03-25

申请号：US16579055

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Szuya S. LIAO ,  Scott B. CLENDENNING ,  Jessica TORRES ,  Lukas BAUMGARTEL ,  Kiran CHIKKADI ,  Diane LANCASTER ,  Matthew V. METZ ,  Florian GSTREIN ,  Martin M. MITAN ,  Rami HOURANI

IPC: H01L27/088 ,  H01L29/423

Abstract: Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.

公开(公告)号：US20210090990A1

公开(公告)日：2021-03-25

申请号：US16579077

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Rami HOURANI ,  Manish CHANDHOK ,  Richard E. SCHENKER ,  Florian GSTREIN ,  Leonard P. GULER ,  Charles H. WALLACE ,  Paul A. NYHUS ,  Curtis WARD ,  Mohit K. HARAN ,  Reken PATEL

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/66

Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.

公开(公告)号：US20210013145A1

公开(公告)日：2021-01-14

申请号：US16955760

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Florian GSTREIN ,  Cen TAN ,  Rami HOURANI

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Etch stop layer-based approaches for via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer, wherein each of the plurality of conductive lines has a bulk portion including a metal and has an uppermost surface including the metal and a non-metal. A hardmask layer is on the plurality of conductive lines and on an uppermost surface of the ILD layer, and includes a first hardmask component on and aligned with the uppermost surface of the plurality of conductive lines, and a second hardmask component on and aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a portion of one of the plurality of conductive lines, the portion having a composition different than the uppermost surface including the metal and the non-metal.

公开(公告)号：US20190318959A1

公开(公告)日：2019-10-17

申请号：US16346305

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Robert L. BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI ,  Marie KRYSAK

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US20180219080A1

公开(公告)日：2018-08-02

申请号：US15506101

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Scott B. CLENDENNING ,  Szuya S. LIAO ,  Florian GSTREIN ,  Rami HOURANI ,  Patricio E. ROMERO ,  Grant M. KLOSTER ,  Martin M. MITAN

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28247 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.

公开(公告)号：US20160351449A1

公开(公告)日：2016-12-01

申请号：US15237542

申请日：2016-08-15

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Rami HOURANI ,  Eungnak HAN ,  James M. BLACKWELL

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/76897 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31051 ,  H01L21/31127 ,  H01L21/76822 ,  H01L21/76834 ,  H01L23/528 ,  H01L23/5328 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.

Abstract translation: 一个方面的方法包括在具有第一图案化区域和第二图案化区域的基底的表面上形成定向自组装对准促进层。 选择性地在第一图案化区域上形成第一定向自组装对准促进材料，而不使用平版印刷图案。 该方法还包括通过定向自组装在定向自组装对准促进层上形成组装层。 形成多个组装结构，每个组合结构主要包括第一类型的自组装排列促进材料上的第一类聚合物。 组装的结构在第二图案化区域上主要围绕第二种不同类型的聚合物。 第一定向自组装校准促进材料对于第一类聚合物具有比对于第二种不同类型的聚合物更大的化学亲和力。