公开(公告)号：US11469323B2

公开(公告)日：2022-10-11

申请号：US16140971

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

公开(公告)号：US11257904B2

公开(公告)日：2022-02-22

申请号：US16024706

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20200098925A1

公开(公告)日：2020-03-26

申请号：US16140971

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

公开(公告)号：US12288807B2

公开(公告)日：2025-04-29

申请号：US18367843

申请日：2023-09-13

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Rishabh Mehandru ,  Willy Rachmady ,  Harold Kennel ,  Tahir Ghani

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/8238

Abstract: A device is disclosed. The device includes a channel, a first source-drain region adjacent a first portion of the channel, the first source-drain region including a first crystalline portion that includes a first region of metastable dopants, a second source-drain region adjacent a second portion of the channel, the second source-drain region including a second crystalline portion that includes a second region of metastable dopants. A gate conductor is on the channel.

公开(公告)号：US11756998B2

公开(公告)日：2023-09-12

申请号：US17576765

申请日：2022-01-14

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/0684 ,  H01L21/02543 ,  H01L21/02546 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7851

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20220416032A1

公开(公告)日：2022-12-29

申请号：US17358436

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Debaleena Nandi ,  Chi-Hing Choi ,  Gilbert Dewey ,  Harold Kennel ,  Omair Saadat ,  Jitendra Kumar Jha ,  Adedapo Oni ,  Nazila Haratipour ,  Anand Murthy ,  Tahir Ghani

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/768

Abstract: Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.

公开(公告)号：US20220199402A1

公开(公告)日：2022-06-23

申请号：US17133079

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Koustav Ganguly ,  Ryan Keech ,  Harold Kennel ,  Willy Rachmady ,  Ashish Agrawal ,  Glenn Glass ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L21/02 ,  H01L29/16 ,  H01L27/092 ,  H01L29/78

Abstract: High-purity Ge channeled N-type transistors include a Si-based barrier material separating the channel from a Ge source and drain that is heavily doped with an N-type impurity. The barrier material may have nanometer thickness and may also be doped with N-type impurities. Because of the Si content, N-type impurities have lower diffusivity within the barrier material and can be prevented from entering high-purity Ge channel material. In addition to Si, a barrier material may also include C. With the barrier material, an N-type transistor may display higher channel mobility and reduced short-channel effects.

公开(公告)号：US11164974B2

公开(公告)日：2021-11-02

申请号：US16631363

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Nancy Zelick ,  Harold Kennel ,  Nicholas G. Minutillo ,  Cheng-Ying Huang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/201 ,  H01L21/8234 ,  H01L27/088

Abstract: A transistor includes a semiconductor fin with a subfin layer of a subfin material selected from a first group III-V compound a channel layer of a channel material directly on the subfin layer and extending upwardly therefrom, the channel material being a second group III-V compound different from the first group III-V compound. A gate structure is in direct contact with the channel layer of the semiconductor fin, where the gate structure is further in direct contact with one of (i) a top surface of the subfin layer, the top surface being exposed where the channel layer meets the subfin layer because the channel layer is narrower than the subfin layer, or (ii) a liner layer of liner material in direct contact with opposing sidewalls of the subfin layer, the liner material being distinct from the first and second group III-V compounds.

公开(公告)号：US20200220017A1

公开(公告)日：2020-07-09

申请号：US16631363

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Nancy Zelick ,  Harold Kennel ,  Nicholas G. Minutillo ,  Cheng-Ying Huang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

Abstract: A transistor includes a semiconductor fin with a subfin layer of a subfin material selected from a first group III-V compound a channel layer of a channel material directly on the subfin layer and extending upwardly therefrom, the channel material being a second group III-V compound different from the first group III-V compound. A gate structure is in direct contact with the channel layer of the semiconductor fin, where the gate structure is further in direct contact with one of (i) a top surface of the subfin layer, the top surface being exposed where the channel layer meets the subfin layer because the channel layer is narrower than the subfin layer, or (ii) a liner layer of liner material in direct contact with opposing sidewalls of the subfin layer, the liner material being distinct from the first and second group III-V compounds.

公开(公告)号：US10170314B2

公开(公告)日：2019-01-01

申请号：US15246468

申请日：2016-08-24

Applicant: Intel Corporation

Inventor： Jacob Jensen ,  Tahir Ghani ,  Mark Y. Liu ,  Harold Kennel ,  Robert James

IPC: H01L21/268 ,  H01L29/417 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L21/324

Abstract: A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.