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公开(公告)号：US10409319B2
公开(公告)日：2019-09-10
申请号：US15488667
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Iqbal R. Rajwani , Altug Koker , Bhushan M. Borole , Kamal Sinha , Abhishek R. Appu , Anupama A. Thaploo , Sunil Nekkanti , Wenyin Fu
Abstract: In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.
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公开(公告)号：US10177765B2
公开(公告)日：2019-01-08
申请号：US15244839
申请日：2016-08-23
Applicant: Intel Corporation
Inventor： Steven K. Hsu , Amit Agarwal , Iqbal R. Rajwani , Simeon Realov , Ram K. Krishnamurthy
IPC: H03K19/00 , H03K19/0944 , H03K19/20
Abstract: An apparatus is provided which comprises: a clock node; a test node; an enable node; and an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionality. Another apparatus comprises: a critical timing path having a pass-gate based integrated clock gate; and a non-critical timing path electrically coupled to the critical timing path, wherein the non-critical timing path includes an AND-OR-Inverter (AOI) based integrated clock gate with embedded NOR functionality.
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公开(公告)号：US10062429B1
公开(公告)日：2018-08-28
申请号：US15488681
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Bhushan Borole , Iqbal R. Rajwani , Anupama A. Thaploo , Sunil Nekkanti , Altug Koker , Abhisek R. Appu
IPC: G11C5/05 , G11C11/4094 , G06F3/06 , G11C11/4074 , G11C11/4093 , G06F13/40 , G06F9/38
CPC classification number: G11C11/4094 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06F9/30123 , G06F9/30141 , G06F9/3851 , G06F9/3867 , G06F9/3887 , G06F12/08 , G06F12/0868 , G06F12/0897 , G06F12/1027 , G06F12/109 , G06F13/4068 , G11C11/4074 , G11C11/4093 , G11C11/419 , Y02D10/14 , Y02D10/151
Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
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公开(公告)号：US20180145663A1
公开(公告)日：2018-05-24
申请号：US15860562
申请日：2018-01-02
Applicant: INTEL CORPORATION
Inventor： Amit Agarwal , Steven K. Hsu , Simeon Realov , Iqbal R. Rajwani , Ram K. Krishnamurthy
IPC: H03K3/3562 , H03K3/037
CPC classification number: H03K3/3562 , H03K3/0372 , H03K3/35625
Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.
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公开(公告)号：US20210065779A1
公开(公告)日：2021-03-04
申请号：US17018071
申请日：2020-09-11
Applicant: Intel Corporation
Inventor： Bhushan M. Borole , Iqbal R. Rajwani , Anupama A. Thaploo , Sunil Nekkanti , Altug Koker , Abhishek R. Appu
IPC: G11C11/4094 , G06F13/40 , G06F9/38 , G06F9/30 , G06F12/0897 , G06F12/0868 , G06F12/109 , G06F12/1027 , G06F3/06 , G11C11/4074 , G11C11/4093 , G06F12/08
Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US10790010B2
公开(公告)日：2020-09-29
申请号：US16435878
申请日：2019-06-10
Applicant: Intel Corporation
Inventor： Bhushan M. Borole , Iqbal R. Rajwani , Anupama A. Thaploo , Sunil Nekkanti , Altug Koker , Abhisek R. Appu
IPC: G11C7/00 , G11C11/4094 , G06F13/40 , G06F9/38 , G06F9/30 , G06F12/0897 , G06F12/0868 , G06F12/109 , G06F12/1027 , G06F3/06 , G11C11/4074 , G11C11/4093 , G06F12/08 , G11C11/419
Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
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公开(公告)号：US20200019207A1
公开(公告)日：2020-01-16
申请号：US16527165
申请日：2019-07-31
Applicant: Intel Corporation
Inventor： Iqbal R. Rajwani , Altug Koker , Bhushan M. Borole , Kamal Sinha , Abhishek R. Appu , Anupama A. Thaploo , Sunil Nekkanti , Wenyin Fu
Abstract: In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.
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公开(公告)号：US10347324B2
公开(公告)日：2019-07-09
申请号：US16054207
申请日：2018-08-03
Applicant: Intel Corporation
Inventor： Bhushan M. Borole , Iqbal R. Rajwani , Anupama A. Thaploo , Sunil Nekkanti , Altug Koker , Abhisek R. Appu
IPC: G11C7/00 , G11C11/4094 , G06F13/40 , G06F9/38 , G06F12/08 , G06F9/30 , G06F3/06 , G11C11/4074 , G11C11/4093 , G11C11/419
Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
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公开(公告)号：US20180300137A1
公开(公告)日：2018-10-18
申请号：US15488947
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Anupama A. Thaploo , Bhushan M. Borole , Bee Ngo , Iqbal R. Rajwani , Altug Koker , Abhishek R. Appu , Kamal Sinha , Wenyin Fu
CPC classification number: G06F9/30105 , G06F13/4068 , G06F13/4077 , G11C7/12 , G11C11/4094 , G11C17/16 , G11C17/18
Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.
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公开(公告)号：US09859876B1
公开(公告)日：2018-01-02
申请号：US15247713
申请日：2016-08-25
Applicant: Intel Corporation
Inventor： Amit Agarwal , Steven K. Hsu , Simeon Realov , Iqbal R. Rajwani , Ram K. Krishnamurthy
IPC: H03K3/3562 , H03K3/037
CPC classification number: H03K3/3562 , H03K3/0372 , H03K3/35625
Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.
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