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    Zero-misalignment two-via structures
    12.
    发明授权
    Zero-misalignment two-via structures 有权

    公开(公告)号：US11222836B2

    公开(公告)日：2022-01-11

    申请号：US16649578

    申请日：2017-12-30

    Applicant: Intel Corporation

    Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Brandon Rawlings ,  Johanna Swan

    IPC: H01L29/40 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/538

    Abstract: Device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS directly coupled to the interconnect. The ZM2VS further includes the dielectric on a conductive pad, a first via on a first seed, and first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS also has a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

    COMPOSITE IC CHIPS INCLUDING A CHIPLET EMBEDDED WITHIN METALLIZATION LAYERS OF A HOST IC CHIP
    13.
    发明申请
    COMPOSITE IC CHIPS INCLUDING A CHIPLET EMBEDDED WITHIN METALLIZATION LAYERS OF A HOST IC CHIP 有权

    公开(公告)号：US20210375830A1

    公开(公告)日：2021-12-02

    申请号：US17399185

    申请日：2021-08-11

    Applicant: Intel Corporation

    Inventor： Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Patrick Morrow ,  Gerald Pasdast ,  Van Le

    IPC: H01L25/065 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00

    Abstract: Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

    Mixed hybrid bonding structures and methods of forming the same
    14.
    发明授权
    Mixed hybrid bonding structures and methods of forming the same 有权

    公开(公告)号：US11183477B2

    公开(公告)日：2021-11-23

    申请号：US16584522

    申请日：2019-09-26

    Applicant: Intel Corporation

    Inventor： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Nagatoshi Tsunoda ,  Jimin Yao

    IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

    Abstract: Embodiments include a mixed hybrid bonding structure comprising a composite dielectric layer, where the composite dielectric layer comprises an organic dielectric material having a plurality of inorganic filler material. One or more conductive substrate interconnect structures are within the composite dielectric layer. A die is on the composite dielectric layer, the die having one or more conductive die interconnect structures within a die dielectric material. The one or more conductive die interconnect structures are directly bonded to the one or more conductive substrate interconnect structures, and the inorganic filler material of the composite dielectric layer is bonded to the die dielectric material.

    ORGANIC INTERPOSERS FOR INTEGRATED CIRCUIT PACKAGES
    16.
    发明申请
    ORGANIC INTERPOSERS FOR INTEGRATED CIRCUIT PACKAGES 有权

    公开(公告)号：US20210082822A1

    公开(公告)日：2021-03-18

    申请号：US16573943

    申请日：2019-09-17

    Applicant: Intel Corporation

    Inventor： Aleksandar Aleksov ,  Henning Braunisch ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong ,  Johanna Swan

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

    Abstract: An electronic interposer may be formed comprising an upper section, a lower section and a middle section. The upper section and the lower section may each have between two and four layers, wherein each layer comprises an organic material layer and at least one conductive route comprising at least one conductive trace and at least one conductive via. The middle section may be formed between the upper section and the lower section, wherein the middle section comprises up to eight layers, wherein each layer comprises an organic material and at least one conductive route comprising at least one conductive trace and at least one conductive via, and wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and thinner than a thickness of any of the layers of the lower section.

    Skip level vias in metallization layers for integrated circuit devices
    19.
    发明授权
    Skip level vias in metallization layers for integrated circuit devices 有权

    公开(公告)号：US12288746B2

    公开(公告)日：2025-04-29

    申请号：US16727747

    申请日：2019-12-26

    Applicant: Intel Corporation

    Inventor： Adel Elsherbini ,  Mauro Kobrinsky ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast ,  Sathya Narasimman Tiagaraj

    IPC: H01L23/52 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

    Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

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