公开(公告)号：US20250103075A1

公开(公告)日：2025-03-27

申请号：US18474156

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Khondker Ahmed ,  Nicolas Butzen ,  Nachiket Desai ,  Su Hwan Kim ,  Harish K. Krishnamurthy ,  Krishnan Ravichandran ,  Kaladhar Radhakrishnan ,  Jonathan Douglas

IPC: G05F1/56

Abstract: Embodiments herein relate to a stacked semiconductor structure which includes a first voltage regulator (VR), external to a package, for supplying current to a compute die in the package. When the required current exceeds a threshold, an additional current source is activated. The additional current source can include a second VR, also external to the package, for supplying current to an integrated voltage regulator (IVR) in the package. The IVR performs voltage down conversion and current multiplication to output a portion of the required current above the threshold, while the output of the first VR is capped at the threshold.

公开(公告)号：US20210271277A1

公开(公告)日：2021-09-02

申请号：US17253096

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Khondker Ahmed ,  Harish Krishnamurthy ,  Krishnan Ravichandran

IPC: G05F1/575 ,  G06F1/26

Abstract: A Computational Digital Low Dropout (CDLDO) regulator is described that computes a required solution for regulating an output supply as opposed to traditional feedback controllers. The CDLDO regulator is Moore's Law friendly in that it can scale with technology nodes. For example, CDLDO regulator of some embodiments uses a digital approach to voltage regulation, which is orders of magnitude faster than traditional digital LDOs and enables regulation at GHz speeds, making fast dynamic DVFS a reality. The CDLDO also autonomously tunes out the effects of process-voltage-temperature (PVT) and other non-idealities making the settling time totally variation tolerant.

公开(公告)号：US20210208656A1

公开(公告)日：2021-07-08

申请号：US16735563

申请日：2020-01-06

Applicant: Intel Corporation

Inventor： Alexander Uan-Zo-Li ,  Eugene Gorbatov ,  Harish Krishnamurthy ,  Alexander Lyakhov ,  Patrick Leung ,  Stephen Gunther ,  Arik Gihon ,  Khondker Ahmed ,  Philip Lehwalder ,  Sameer Shekhar ,  Vishram Pandit ,  Nimrod Angel ,  Michael Zelikson

IPC: G06F1/32 ,  G05F1/56

Abstract: A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

公开(公告)号：US10298117B2

公开(公告)日：2019-05-21

申请号：US15638643

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： Harish Krishnamurthy ,  Khondker Ahmed ,  Vivek De ,  Nachiket Desai ,  Suhwan Kim ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram Vangal

IPC: H04W84/20 ,  H02M1/42 ,  H03M1/00 ,  H02M1/00 ,  H02M1/084 ,  H02M3/158

Abstract: Embodiments described herein describe operating a master-slave controller. Operating the master-slave controller comprises, based on a determination that the first output voltage value is greater than the second output voltage value, calculating a first duty cycle value and an input voltage value and the second voltage regulator, calculating a second duty cycle value based on the first duty cycle value, and based on a determination that the second output voltage value is greater than or equal to the first output voltage value, calculating the second duty cycle value based on the second output voltage value and the input voltage value and calculating the first duty cycle value based on the second duty cycle value and configuring the first voltage regulator with the first duty cycle value and the second voltage regulator with the second duty cycle value.

公开(公告)号：US20180375433A1

公开(公告)日：2018-12-27

申请号：US15632086

申请日：2017-06-23

Applicant: INTEL CORPORATION

Inventor： Khondker Ahmed ,  Vivek De ,  Nachiket Desai ,  Suhwan Kim ,  Harish Krishnamurthy ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram Vangal

IPC: H02M3/158 ,  H02M1/08

CPC classification number: H02M3/1582 ,  G05F1/67 ,  H02M1/08 ,  H02M2001/0003 ,  H02M2001/0009 ,  H02M2001/0025

Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.