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    INTEGRATED SETBACK READ WITH REDUCED SNAPBACK DISTURB
    11.
    发明申请
    INTEGRATED SETBACK READ WITH REDUCED SNAPBACK DISTURB 审中-公开
    集成的SETBACK读取与减少的反应障碍

    公开(公告)号：US20160372193A1

    公开(公告)日：2016-12-22

    申请号：US15180556

    申请日：2016-06-13

    Applicant: Intel Corporation

    Inventor： Arjun Kripanidhi ,  Kiran Pangal ,  Lark-Hoon Leem ,  Balaji Srinivasan

    IPC: G11C13/00

    CPC classification number: G11C13/0033 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0052 ,  G11C2013/0066

    Abstract: Embodiments of the present disclosure describe read and write operations in phase change memory to reduce snapback disturb. In an embodiment, an apparatus includes read circuitry to apply a read voltage to a phase change memory (PCM) cell, setback circuitry to apply a setback pulse to the PCM cell in response to the application of the read voltage, wherein the setback pulse is a shorter set pulse performed for a first period of time that is shorter than a second period of time for a regular set pulse that is configured to transition the PCM cell from an amorphous state to a crystalline state, sense circuitry to sense, concurrently with application of the setback pulse, whether the PCM cell is in the amorphous state or the crystalline state. Other embodiments may be described and/or claimed.

    Abstract translation: 本公开的实施例描述了在相变存储器中的读取和写入操作以减少突发干扰。 在一个实施例中，一种装置包括读取电路，用于将读取电压施加到相变存储器（PCM）单元，响应于读取电压的应用，将回退脉冲施加到PCM单元，其中挫折脉冲是 对于被配置为将PCM单元从非晶状态转换为结晶状态的规则设定脉冲，对于比第二时间段短的第一时间段执行的更短的设定脉冲，感测电路与应用同时感测 的挫折脉冲，PCM单元是处于非晶态还是结晶状态。 可以描述和/或要求保护其他实施例。

    PHASE CHANGE MEMORY CURRENT
    12.
    发明申请
    PHASE CHANGE MEMORY CURRENT 有权
    相变记忆电流

    公开(公告)号：US20160351258A1

    公开(公告)日：2016-12-01

    申请号：US14725826

    申请日：2015-05-29

    Applicant: Intel Corporation

    Inventor： Mase J. Taub ,  Sandeep K. Guliani ,  Kiran Pangal ,  Raymond W. Zeng

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/72 ,  G11C2213/76 ,  G11C2213/79

    Abstract: The present disclosure relates to phase change memory current. An apparatus includes a memory controller including a word line (WL) control module and a bit line (BL) control module, the memory controller is to initiate selection of a memory cell. The apparatus further includes a mitigation module to configure a first line selection logic to reduce a transient energy dissipation of the memory cell, the transient energy related to selecting the memory cell.

    Abstract translation: 本公开涉及相变存储器电流。 一种装置包括一个包括字线（WL）控制模块和位线（BL）控制模块的存储器控​​制器，该存储器控制器开始选择一个存储单元。 该装置还包括缓解模块，用于配置第一线路选择逻辑以减少存储器单元的瞬态能量耗散，与选择存储器单元有关的瞬态能量。

    MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY
    14.
    发明申请
    MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY 有权
    相变存储器的多级设置步骤

    公开(公告)号：US20160284404A1

    公开(公告)日：2016-09-29

    申请号：US14672130

    申请日：2015-03-28

    Applicant: Intel Corporation

    Inventor： Sanjay Rangan ,  Kiran Pangal ,  Nevil N Gajera ,  Lu Liu ,  Gayathri Rao Subbu

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C11/16 ,  G11C13/0004 ,  G11C13/0061 ,  G11C2013/0078 ,  G11C2013/008 ,  G11C2013/0092 ,  H01L45/06 ,  H01L45/1286 ,  H01L45/141

    Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

    Abstract translation: 相变材料可以通过多级设定过程进行设置。 设置控制逻辑可以将相变半导体材料（PM）加热到第一温度一段时间。 第一温度被配置成促进PM的结晶状态的成核。 控制逻辑可以将温度升高到第二温度持续第二时间段。 第二温度被配置为促进PM内的晶体生长。 晶体的成核和生长将PM设置为结晶状态。 相对于传统方法，多级升温可以提高设定过程的效率。

    EXTENDED SELECT GATE LIFETIME
    16.
    发明申请
    EXTENDED SELECT GATE LIFETIME 有权

    公开(公告)号：US20150213900A1

    公开(公告)日：2015-07-30

    申请号：US14679574

    申请日：2015-04-06

    Applicant: Intel Corporation

    Inventor： Yogesh B. Wakchaure ,  Kiran Pangal ,  Xin Guo ,  Qingru Meng ,  Hanmant P. Belgal

    IPC: G11C16/14 ,  G11C16/34 ,  G11C16/04

    CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3445 ,  G11C29/028 ,  H01L27/115

    Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range.

    Techniques to mitigate error during a read operation to a memory array
    17.
    发明授权
    Techniques to mitigate error during a read operation to a memory array 有权

    公开(公告)号：US11145366B1

    公开(公告)日：2021-10-12

    申请号：US16828860

    申请日：2020-03-24

    Applicant: Intel Corporation

    Inventor： Davide Mantegazza ,  Kiran Pangal

    IPC: G11C11/00 ,  G11C13/00 ,  G11C29/12 ,  G11C29/50 ,  G11C29/44

    Abstract: Examples may include techniques to mitigate errors during a read operation to a memory cell of a memory array. Examples include selecting the memory cell and applying one of multiple demarcation read voltages for respective multiple time intervals to sense a state of a resistive storage element of the memory cell. Examples also include applying a bias voltage to the memory cell following a sense interval to mitigate read disturb to the resistive storage element incurred while the one of the multiple demarcation read voltages was applied to the memory cell.

    Cross point memory control
    18.
    发明授权
    Cross point memory control 有权

    公开(公告)号：US10546634B2

    公开(公告)日：2020-01-28

    申请号：US16140441

    申请日：2018-09-24

    Applicant: Intel Corporation

    Inventor： Raymond W. Zeng ,  Mase J. Taub ,  Kiran Pangal ,  Sandeep K. Guliani

    IPC: G11C13/00 ,  G11C8/06 ,  G11C16/08 ,  G11C16/34

    Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.

    Cross point memory control
    20.
    发明授权
    Cross point memory control 有权

    公开(公告)号：US10134468B2

    公开(公告)日：2018-11-20

    申请号：US15465470

    申请日：2017-03-21

    Applicant: Intel Corporation

    Inventor： Raymond W. Zeng ,  Mase J. Taub ,  Kiran Pangal ,  Sandeep K. Guliani

    IPC: G11C13/00

    Abstract: The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.

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