公开(公告)号：US20200312989A1

公开(公告)日：2020-10-01

申请号：US16365018

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Hubert C. George ,  Sarah Atanasov ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  David J. Michalak ,  Jeanette M. Roberts ,  Stephanie A. Bojarski

IPC: H01L29/775 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  G06N10/00

Abstract: Disclosed herein are quantum dot devices with multiple layers of gate metal, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material above the quantum well stack, wherein the insulating material includes a trench; and a gate on the insulating material and extending into the trench, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal.

公开(公告)号：US20200312963A1

公开(公告)日：2020-10-01

申请号：US16367155

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Stephanie A. Bojarski ,  Hubert C. George ,  Sarah Atanasov ,  Nicole K. Thomas ,  Ravi Pillarisetty ,  Lester Lampert ,  Thomas Francis Watson ,  David J. Michalak ,  Roman Caudillo ,  Jeanette M. Roberts ,  James S. Clarke

IPC: H01L29/12 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  G06N10/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack and a plurality of linear arrays of gates above the quantum well stack to control quantum dot formation in the quantum well stack. An insulating material may be between a first linear array of gates and a second linear array of gates, the insulating material may be between individual gates in the first linear array of gates, and gate metal of the first linear array of gates may extend over the insulating material.

公开(公告)号：US20190334020A1

公开(公告)日：2019-10-31

申请号：US16349955

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Payam Amin ,  Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Hubert C. George ,  Kanwaljit Singh ,  Van H. Le ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  David J. Michalak

IPC: H01L29/775 ,  H01L29/12 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  G06N10/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.

公开(公告)号：US20190273197A1

公开(公告)日：2019-09-05

申请号：US16347097

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Adel A. Elsherbini ,  Shawna Liff ,  Johanna M. Swan ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Ravi Pillarisetty ,  Hubert C. George ,  James S. Clarke

IPC: H01L39/04 ,  G06N10/00 ,  H01L39/02 ,  H01L39/22 ,  H01L39/24

Abstract: One superconducting qubit device package disclosed herein includes a die having a first face and an opposing second face, and a package substrate having a first face and an opposing second face. The die includes a quantum device including a plurality of superconducting qubits and a plurality of resonators on the first face of the die, and a plurality of conductive pathways coupled between conductive contacts at the first face of the die and associated ones of the plurality of superconducting qubits or of the plurality of resonators. The second face of the package substrate also includes conductive contacts. The device package further includes first level interconnects disposed between the first face of the die and the second face of the package substrate, coupling the conductive contacts at the first face of the die with associated conductive contacts at the second face of the package substrate.

公开(公告)号：US20190164959A1

公开(公告)日：2019-05-30

申请号：US16320773

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Jeanette M. Roberts ,  Hubert C. George ,  James S. Clarke

IPC: H01L27/06 ,  G06N10/00 ,  H01L27/18 ,  H01L29/66 ,  H01L29/76 ,  H01L39/22 ,  H01L29/12 ,  H01L29/778 ,  H01L39/24

Abstract: Described herein are quantum integrated circuit (IC) assemblies that include quantum circuit components comprising a plurality of qubits and control logic coupled to the quantum circuit components and configured to control operation of those components, where the quantum circuit component(s) and the control logic are provided on a single die. By implementing control logic on the same die as the quantum circuit component(s), more functionality can be provided on-chip, thus integrating more of signal chain on-chip. Integration can greatly reduce complexity and lower the cost of quantum computing devices, reduce interfacing bandwidth, and provide an approach that can be efficiently used in large scale manufacturing. Methods for fabricating such assemblies are also disclosed.

公开(公告)号：US20190140073A1

公开(公告)日：2019-05-09

申请号：US16097432

申请日：2016-06-08

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Jeanette M. Roberts ,  Hubert C. George ,  James S. Clarke ,  Nicole K. Thomas

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L29/12 ,  H01L29/165 ,  H01L29/778

CPC classification number: H01L29/66431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/127 ,  H01L29/165 ,  H01L29/423 ,  H01L29/42376 ,  H01L29/66977 ,  H01L29/7613 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/785

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of first gates disposed on the quantum well stack; a plurality of pairs of spacers, each pair of spacers disposed on opposites sides of an associated first gate, wherein each spacer in a pair has a curved surface that curves away from the associated first gate; and a plurality of second gates disposed on the quantum well stack, wherein the curved surface of each spacer is adjacent to one of the second gates such that at least a portion of each second gate is shaped complementarily to the curved surface of an adjacent spacer.

公开(公告)号：US20190044051A1

公开(公告)日：2019-02-07

申请号：US16102780

申请日：2018-08-14

Applicant: Intel Corporation

Inventor： Roman Caudillo ,  Lester Lampert ,  David J. Michalak ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  Hubert C. George ,  Nicole K. Thomas ,  James S. Clarke

IPC: H01L39/22 ,  H01L39/02 ,  H01L39/24 ,  H01L27/18 ,  H01L39/04 ,  G06N99/00

Abstract: Embodiments of the present disclosure relate to quantum circuit assemblies implementing superconducting qubits, e.g., transmons, in which SQUID loops and portions of FBLs configured to magnetically couple to the SQUID loops extend substantially vertically. In contrast to conventional implementations, for a vertical SQUID according to various embodiments of the present disclosure, a line that is perpendicular to the SQUID loop is parallel to the qubit substrate. A corresponding FBL is also provided in a vertical arrangement, in order to achieve efficient magnetic coupling to the vertical SQUID loop, by ensuring that at least a portion of the FBL designed to conduct current responsible for generating magnetic field for tuning qubit frequency is substantially perpendicular to the substrate.

公开(公告)号：US20190044045A1

公开(公告)日：2019-02-07

申请号：US15924410

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Lester Lampert ,  Ravi Pillarisetty ,  Hubert C. George ,  Kanwaljit Singh ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  David J. Michalak

IPC: H01L39/02 ,  H01L39/04 ,  H01L39/22 ,  H01L39/24 ,  H03K17/92 ,  G06N99/00

CPC classification number: H01L39/025 ,  B82Y10/00 ,  G06N10/00 ,  H01L29/127 ,  H01L29/423 ,  H01L29/66439 ,  H01L29/66977 ,  H01L29/66984 ,  H01L29/7613 ,  H01L39/045 ,  H01L39/223 ,  H01L39/249 ,  H01L39/2493 ,  H03K17/92

Abstract: Embodiments of the present disclosure describe use of isotopically purified materials in donor- or acceptor-based spin qubit devices and assemblies. An exemplary spin qubit device assembly may include a semiconductor host layer that includes an isotopically purified material, a dopant atom in the semiconductor host layer, and a gate proximate to the dopant atom. An isotopically purified material may include a lower atomic-percent of isotopes with nonzero nuclear spin than the natural abundance of those isotopies in the non-isotopically purified material. Reducing the presence of isotopes with nonzero nuclear spin in a semiconductor host layer may improve qubit coherence and thus performance of spin qubit devices and assemblies.

公开(公告)号：US20190043975A1

公开(公告)日：2019-02-07

申请号：US16017031

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Hubert C. George ,  David J. Michalak ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  Jeanette M. Roberts

IPC: H01L29/778 ,  H01L29/12 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/15 ,  H01L27/088 ,  H01L29/10 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a first dielectric material around a bottom portion of the fin; and a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material.

公开(公告)号：US20190043968A1

公开(公告)日：2019-02-07

申请号：US15924407

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Lester Lampert ,  James S. Clarke ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Kanwaljit Singh ,  Roman Caudillo ,  Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas

IPC: H01L29/66 ,  H01L29/82 ,  H01L29/49 ,  H01L21/265 ,  H01L29/40 ,  G06N99/00

Abstract: Embodiments of the present disclosure describe a method of fabricating spin qubit device assemblies that utilize dopant-based spin qubits, i.e. spin qubit devices which operate by including a donor or an acceptor dopant atom in a semiconductor host layer. The method includes, first, providing a pair of gate electrodes over a semiconductor host layer, and then providing a window structure between the first and second gate electrodes, the window structure being a continuous solid material extending between the first and second electrodes and covering the semiconductor host layer except for an opening through which a dopant atom is to be implanted in the semiconductor host layer. By using a defined gate-first process, the method may address the scalability challenges and create a deterministic path for fabricating dopant-based spin qubits in desired locations, promoting wafer-scale integration of dopant-based spin qubit devices for use in quantum computing devices.