-
11.发明申请公开(公告)号：US20220261357A1
公开(公告)日：2022-08-18
申请号：US17734994
申请日：2022-05-02
Applicant: Intel Corporation
Inventor： Ronen Gabbai , Amit Bleiweiss , Ohad Falik , Amit Gur , Almog Tzabary
IPC: G06F12/128 , G06F12/0891 , G06F12/126 , G06K9/62
Abstract: Systems, apparatuses, and methods include technology that determines, with a neural network, that a first eviction node stored in a cache will be evicted from the cache based on a cache policy. The first eviction node is part of a plurality of nodes associated with a graph. Further, a subset of nodes of the plurality of nodes remains in the cache after the eviction of the first eviction node from the cache. The technology further tracks a number of cache hits on the cache during an aggregation operation associated with a hardware accelerator, where the aggregation operation is executed on the subset of nodes that remain in the cache after the eviction of the eviction node from the cache. The technology executes a training process on the neural network to adjust the cache policy based on the number of the cache hits.
-
公开(公告)号：US10708328B2
公开(公告)日：2020-07-07
申请号：US14215940
申请日：2014-03-17
Applicant: INTEL CORPORATION
Inventor： Christopher Hall , Kevin B. Stanton , Pierre-Louis Bossart , Anthony S. Bock , Ohad Falik
Abstract: Techniques to output a media stream, capture a media stream, or synchronize the output or capture of the media stream at a specified time are described. A media stream output or capture apparatus may include a media processor to receive a media stream to output or a request to capture a media stream and a start time. A buffer generator may be included to generate an input or an output buffer and a media mixer may be included to mix the media stream into the output buffer at the start time or capture the media stream from the input buffer at the start time.
-
公开(公告)号：US10672401B2
公开(公告)日：2020-06-02
申请号：US15198193
申请日：2016-06-30
Applicant: INTEL CORPORATION
Inventor： Nikhil Pantpratinidhi , Gokcen Cilingir , Michael Deisher , Ohad Falik , Michael Kounavis
Abstract: Systems, apparatus and methods are described including operations for a dual mode GMM (Gaussian Mixture Model) scoring accelerator for both speech and video data.
-
公开(公告)号：US20170010648A1
公开(公告)日：2017-01-12
申请号：US15270206
申请日：2016-09-20
Applicant: Intel Corporation
Inventor： Shaun M. Conrad , William Knolla , Douglas R. Moran , Sm M. Rahman , Jawad Haj-Yihia , Alon Naveh , Ohad Falik
CPC classification number: G06F1/3206 , G06F1/3237 , G06F1/324 , G06F1/3296 , G06F13/40 , G06F13/4027 , G06F13/4068 , Y02D10/126 , Y02D10/128 , Y02D10/151 , Y02D10/172
Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.
Abstract translation: 处理器包括至少一个核心，功率控制单元和与外围控制器耦合的第一互连。 第一互连是提供用于从处理器到外围控制器的第一电力管理数据的通信的第一单向通信路径。 描述和要求保护其他实施例。
-
公开(公告)号：US09442855B2
公开(公告)日：2016-09-13
申请号：US14583601
申请日：2014-12-27
Applicant: Intel Corporation
Inventor： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
CPC classification number: G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
Abstract translation: 这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。 提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。 包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。 提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。 包括有功功率子状态及其设置以允许更有效的电源管理。 并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。
-
Patent Agency Ranking
16.发明申请公开(公告)号：US20160041921A1
公开(公告)日：2016-02-11
申请号：US14886822
申请日：2015-10-19
Applicant: Intel Corporation
Inventor： Ben-Zion Friedman , Jacob Doweck , Eliezer Weissmann , James B Crossland , Ohad Falik
IPC: G06F12/10
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
Abstract translation: 本发明的实施例一般涉及用于线性到物理地址转换的系统，方法和装置，其支持页面属性。 在一些实施例中，系统接收将存储器指针转换为存储器位置的物理存储器地址的指令。 系统可以返回物理内存地址和一个或多个页面属性。 描述和要求保护其他实施例。
-
公开(公告)号：US09164916B2
公开(公告)日：2015-10-20
申请号：US14455072
申请日：2014-08-08
Applicant: Intel Corporation
Inventor： Ohad Falik , Ben-Zion Friedman , Jacob Doweck , Eliezer Weissmann , James B Crossland
CPC classification number: G06F12/1009 , G06F12/10 , G06F12/1027 , G06F12/1036 , G06F2212/1016 , G06F2212/507 , G06F2212/65 , G06F2212/657 , G06F2212/68
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
-
公开(公告)号：US20140351553A1
公开(公告)日：2014-11-27
申请号：US14455072
申请日：2014-08-08
Applicant: Intel Corporation
Inventor： Ohad Falik , Ben-Zion Friedman , Jacob Doweck , Eliezer Weissmann , James B Crossland
IPC: G06F12/10
CPC classification number: G06F12/1009 , G06F12/10 , G06F12/1027 , G06F12/1036 , G06F2212/1016 , G06F2212/507 , G06F2212/65 , G06F2212/657 , G06F2212/68
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.
-
公开(公告)号：US08806068B2
公开(公告)日：2014-08-12
申请号：US13706575
申请日：2012-12-06
Applicant: Intel Corporation
Inventor： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
-
公开(公告)号：US11151074B2
公开(公告)日：2021-10-19
申请号：US16542085
申请日：2019-08-15
Applicant: Intel Corporation
Inventor： Israel Diamand , Roni Rosner , Ravi Venkatesan , Shlomi Shua , Oz Shitrit , Henrietta Bezbroz , Alexander Gendler , Ohad Falik , Zigi Walter , Michael Behar , Shlomi Alkalay
IPC: G06F13/42 , G06N3/04 , G06F13/20 , G06F12/0893
Abstract: Methods and apparatus to implement multiple inference compute engines are disclosed herein. A disclosed example apparatus includes a first inference compute engine, a second inference compute engine, and an accelerator on coherent fabric to couple the first inference compute engine and the second inference compute engine to a converged coherency fabric of a system-on-chip, the accelerator on coherent fabric to arbitrate requests from the first inference compute engine and the second inference compute engine to utilize a single in-die interconnect port.
-
-
-
-
-
-
-
-
-
Search Results
34
records
(took 0.023 seconds)
