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    FIELD EFFECT TRANSISTORS WITH A GATED OXIDE SEMICONDUCTOR SOURCE/DRAIN SPACER
    11.
    发明申请
    FIELD EFFECT TRANSISTORS WITH A GATED OXIDE SEMICONDUCTOR SOURCE/DRAIN SPACER 有权

    公开(公告)号：US20220028998A1

    公开(公告)日：2022-01-27

    申请号：US17498614

    申请日：2021-10-11

    Applicant: Intel Corporation

    Inventor： Gilbert W. Dewey ,  Rafael Rios ,  Van H. Le ,  Jack T. Kavalieros

    IPC: H01L29/49 ,  H01L27/092 ,  H01L21/28

    Abstract: FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.

    Two transistor, one resistor non-volatile gain cell memory and storage element
    12.
    发明授权
    Two transistor, one resistor non-volatile gain cell memory and storage element 有权

    公开(公告)号：US10950301B2

    公开(公告)日：2021-03-16

    申请号：US16320023

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Rafael Rios ,  Abhishek Anil Sharma ,  Van H. Le ,  Gilbert William Dewey ,  Jack T. Kavalieros

    IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24 ,  G11C8/16

    Abstract: A two transistor, one resistor gain cell and a suitable storage element are described. In some embodiments the gain cell has a resistive memory element coupled to a common node at one end to store a value and to a source line at another end, the value being read as conductivity between the common node and the source line of the resistive memory element, a write transistor having a source coupled to a bit line, a gate coupled to a write line, and a drain coupled to the common node to write a value at the bit line to the resistive memory element upon setting the write line high, and a read transistor having a source coupled to a bit line read line and a gate coupled to the common node to read the value written to the resistive memory element as a value at the second transistor gate.

    Flip-flop circuit with low-leakage transistors
    14.
    发明授权
    Flip-flop circuit with low-leakage transistors 有权

    公开(公告)号：US10423203B2

    公开(公告)日：2019-09-24

    申请号：US15392559

    申请日：2016-12-28

    Applicant: Intel Corporation

    Inventor： Charles Augustine ,  Rafael Rios ,  Somnath Paul ,  Muhammad M. Khellah

    IPC: G06F1/26 ,  H03K3/012 ,  G06F1/3293 ,  H03K3/356

    Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.

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