公开(公告)号：US20220229724A1

公开(公告)日：2022-07-21

申请号：US17715771

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Rajat AGARWAL ,  Jongwon LEE

IPC: G06F11/10

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

公开(公告)号：US20210336767A1

公开(公告)日：2021-10-28

申请号：US17359152

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Raghunandan MAKARAM ,  Kirk S. YAP ,  Rajat AGARWAL ,  George VERGIS ,  Bill NALE ,  Jacob DOWECK

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/32 ,  G11C29/42 ,  G11C29/12

Abstract: A memory subsystem includes link encryption for the system memory data bus. The memory controller can provide encryption for data at rest and link protection. The memory controller can optionally provide link encryption. Thus, the system can provide link protection for the data in transit. The memory module can include a link decryption engine that can decrypt link encryption if it is used, and performs a link integrity check with a link integrity tag associated with the link protection. The memory devices can then store the encrypted protected data and ECC data from the link decryption engine after link protection verification.

公开(公告)号：US20200278906A1

公开(公告)日：2020-09-03

申请号：US16875642

申请日：2020-05-15

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Rajat AGARWAL ,  Jongwon LEE

IPC: G06F11/10 ,  G11C11/4096

Abstract: A memory device that performs internal ECC (error checking and correction) can selectively return read data with application of the internal ECC or without application of the internal ECC, in response to different read commands from the memory controller. The memory device can normally apply ECC and return corrected data in response to a normal read command. In response to a retry command, the memory device can return the read data without application of the internal ECC.

公开(公告)号：US20190171568A1

公开(公告)日：2019-06-06

申请号：US16258486

申请日：2019-01-25

Applicant: INTEL CORPORATION

Inventor： Wei CHEN ,  Rajat AGARWAL ,  Jing LING ,  Daniel W. LIU

IPC: G06F12/0808 ,  G06F12/0866 ,  G06F12/06 ,  G06F12/128 ,  G06F12/0811 ,  G06F1/3287 ,  G06F3/06 ,  G06F12/0868

Abstract: Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the first memory includes at least one RAS controller to read a range of addresses in the first memory. In response to receiving a command from the power control unit, the at least one RAS controller is invoked to read data from at least one range of addresses specified for the RAS controller from the first memory. A second memory controller transfers data read from the first memory determined to be modified to the second memory. The first memory controller sends a signal to the power control unit to indicate that the modified data in the range of addresses specified for the RAS controller was flushed to the second memory in response to the RAS controller completing reading the range of addresses.

公开(公告)号：US20190042499A1

公开(公告)日：2019-02-07

申请号：US16017430

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Rajat AGARWAL ,  George VERGIS ,  Bill NALE

IPC: G06F13/16 ,  G06F13/28

Abstract: A DIMM is described. The DIMM includes circuitry to simultaneously transfer data of different ranks of memory chips on the DIMM over a same data bus during a same burst write sequence.

公开(公告)号：US20190042095A1

公开(公告)日：2019-02-07

申请号：US16111156

申请日：2018-08-23

Applicant: Intel Corporation

Inventor： George VERGIS ,  Bill NALE ,  Derek A. THOMPSON ,  James A. McCALL ,  Rajat AGARWAL ,  Wei P. CHEN

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes a memory controller having register space to inform the memory controller that the memory controller is coupled to a memory module that conforms to a first memory chip industry standard specification but is composed of memory chips that conform to a second, different memory chip industry standard specification.

公开(公告)号：US20240211344A1

公开(公告)日：2024-06-27

申请号：US18025868

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Kjersten E. CRISS ,  Rajat AGARWAL ,  Omar AVELAR SUAREZ ,  Subhankar PANDA ,  Theodros YIGZAW ,  Rebecca Z. LOOP ,  John G. HOLM ,  Gaurav PORWAL

IPC: G06F11/10 ,  G11C29/02

CPC classification number: G06F11/106 ,  G11C29/02

Abstract: A memory subsystem with error checking and scrubbing (ECS) logic on-device on the memory can adapt the rate of ECS operations in response to detection of errors in the memory when the memory device is in automatic ECS mode. The ECS logic can include an indication of rows of memory that have been offlined by the host. The ECS logic can skip the offlined rows in ECS operation counts. The ECS logic can include requests or hints by the host to have ECS operations performed. An internal address generator of the ECS logic can select between generated addresses and the hints. The system can allow a memory controller to detect multibit errors (MBEs) related to a specific address of the associated memory. When the detected MBEs indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.

公开(公告)号：US20240061741A1

公开(公告)日：2024-02-22

申请号：US18268956

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Rajat AGARWAL ,  Hsing-Min CHEN ,  Wei P. CHEN ,  Wei WU ,  Jing LING ,  Kuljit S. BAINS ,  Kjersten E. CRISS ,  Deep K. BUCH ,  Theodros YIGZAW ,  John G. HOLM ,  Andrew M. RUDOFF ,  Vaibhav SINGH ,  Sreenivas MANDAVA

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

公开(公告)号：US20220350500A1

公开(公告)日：2022-11-03

申请号：US17855688

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Wei P. CHEN ,  Theodros YIGZAW ,  Sarathy JAYAKUMAR ,  Anthony LUCK ,  Deep K. BUCH ,  Rajat AGARWAL ,  Kuljit S. BAINS ,  John G. HOLM ,  Brent CHARTRAND ,  Keith KLAYMAN

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes a processor. The processor includes a memory controller to read and write from a memory. The memory controller includes error correction coding (ECC) circuitry to correct errors in data read from the memory. The processor includes register space to track read data error information. The processor includes an embedded controller. The processor includes local memory coupled to the embedded controller. The embedded controller is to read the read data error information and store the read data error information in the local memory.

公开(公告)号：US20200211969A1

公开(公告)日：2020-07-02

申请号：US16235879

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Dheeraj SUBBAREDDY ,  Robert SANKMAN ,  Ravindranath V. MAHAJAN ,  Debendra MALLIK ,  Ram S. VISWANATH ,  Sandeep B. SANE ,  Sriram SRINIVASAN ,  Rajat AGARWAL ,  Aravind DASU ,  Scott WEBER ,  Ravi GUTALA

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.