公开(公告)号：US20210272892A1

公开(公告)日：2021-09-02

申请号：US16804516

申请日：2020-02-28

Applicant: Intel Corporation

Inventor： Zhichao ZHANG ,  Zhe CHEN ,  Srikant NEKKANTY ,  Sriram SRINIVASAN

IPC: H01L23/498 ,  H01L23/58

Abstract: Embodiments include assemblies. An assembly includes a substrate having a first interconnect and a second interconnect. The first interconnect has a first conductive pad and a second conductive pad, and the second interconnect has a third conductive pad and a fourth conductive pad. The assembly includes a socket over the substrate. The socket has a first pin, a second pin, and a base layer with a first pad and a second pad. The first and second pins are vertically over the respective first and second interconnects. The first pad is directly coupled to the first pin and fourth conductive pad, while the second pad is directly coupled to the second pin and second conductive pad. The first pad is positioned partially within a footprint of the third conductive pad, and the second pad is positioned partially within a footprint of the first conductive pad.

公开(公告)号：US20240145395A1

公开(公告)日：2024-05-02

申请号：US18406018

申请日：2024-01-05

Applicant: Intel Corporation

Inventor： MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Dheeraj SUBBAREDDY ,  Robert SANKMAN ,  Ravindranath V. MAHAJAN ,  Debendra MALLIK ,  Ram S. VISWANATH ,  Sandeep B. SANE ,  Sriram SRINIVASAN ,  Rajat AGARWAL ,  Aravind DASU ,  Scott WEBER ,  Ravi GUTALA

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L25/18 ,  H01L23/481 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US20210305138A1

公开(公告)日：2021-09-30

申请号：US16828466

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Zhichao ZHANG ,  Zhenguo JIANG ,  Haifa HARIRI ,  Kemal AYGÜN ,  Sriram SRINIVASAN

IPC: H01L23/498 ,  H01R12/71

Abstract: Embodiments disclosed herein include electronic packaged assemblies. In an embodiment, an electronic package comprises first and second surfaces. The second surface has a land pad in a land pad opening. The land pad is spaced away from the land pad opening by an outer gap. The land pad is a closed loop. In an embodiment, the electronic package is electrically coupled to a socket. The socket has an interconnect with a first connector and a second connector. The first connector of the interconnect is directly coupled to at least one portion of the closed loop. In an embodiment, when the first connector is coupled to at least two or more portions of the closed loop, the portions are spaced away from each other by a portion of the inner or outer gap. The closed loop comprises a conductive line continuously extending from a first end to a second end.

公开(公告)号：US20230089093A1

公开(公告)日：2023-03-23

申请号：US17482804

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Srinivas V. PIETAMBARAM ,  Tarek A. IBRAHIM ,  Krishna BHARATH ,  Bharat PENMECHA ,  Anderw COLLINS ,  Kaladhar RADHAKRISHNAN ,  Sriram SRINIVASAN

IPC: H01F27/28 ,  H01F27/24 ,  H01F41/04

Abstract: Embodiments disclosed herein include electronic packages and methods of assembling such electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a plug is formed through the core, where the plug comprises a magnetic material. In an embodiment, an inductor is around the plug. In an embodiment, first layers are over the core, wherein where the first layers comprise a dielectric material; and second layers are under the core, where the second layers comprise the dielectric material.

公开(公告)号：US20200211969A1

公开(公告)日：2020-07-02

申请号：US16235879

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Dheeraj SUBBAREDDY ,  Robert SANKMAN ,  Ravindranath V. MAHAJAN ,  Debendra MALLIK ,  Ram S. VISWANATH ,  Sandeep B. SANE ,  Sriram SRINIVASAN ,  Rajat AGARWAL ,  Aravind DASU ,  Scott WEBER ,  Ravi GUTALA

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US20200066641A1

公开(公告)日：2020-02-27

申请号：US16305012

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Richard J. DISCHLER ,  Jeff C. MORRISS ,  Zhiguo QIAN ,  Wilfred GOMES ,  Yu Amos ZHANG ,  Ram S. VISWANATH ,  Rajasekaran SWAMINATHAN ,  Sriram SRINIVASAN ,  Yidnekachew S. MEKONNEN ,  Sanka GANESAN ,  Eduard ROYTMAN ,  Mathew J. MANUSHAROW

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L23/60

Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.