公开(公告)号：US11934249B2

公开(公告)日：2024-03-19

申请号：US17710525

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Zhongsheng Wang ,  Chris Binns ,  Deepak Samuel Kirubakaran ,  Ashraf H Wadaa ,  Rajshree Chabukswar ,  Ahmed Shams ,  Sze Ling Yeap ,  Refael Mizrahi ,  Nicholas Klein

IPC: G06F1/3234 ,  G06F9/50 ,  G06F11/30 ,  G06N20/00

CPC classification number: G06F1/3234 ,  G06F9/5094 ,  G06F11/3062 ,  G06N20/00

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, a compute device to manage energy usage and compute performance includes at least one memory, instructions, and processor circuitry. The processor circuitry executes the instructions to determine a system power mode based on first telemetry data associated with the compute device. The processor circuitry executes the instructions to provide user activity data and second telemetry data associated with the compute device to a classification system. The processor circuitry executes the instructions to configure a plurality of parameters to manage power consumption and performance of the compute device based on a classification by the classification system.

公开(公告)号：US11593154B2

公开(公告)日：2023-02-28

申请号：US16228136

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： Ahmad Samih ,  Rajshree Chabukswar ,  Russell Fenger ,  Shadi Khasawneh ,  Vijay Dhanraj ,  Muhammad Abozaed ,  Mukund Ramakrishna ,  Atsuo Kuwahara ,  Guruprasad Settuvalli ,  Eugene Gorbatov ,  Monica Gupta ,  Christine M. Lin

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50 ,  G06F9/30

Abstract: The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

公开(公告)号：US20220221925A1

公开(公告)日：2022-07-14

申请号：US17710525

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Zhongsheng Wang ,  Chris Binns ,  Deepak Samuel Kirubakaran ,  Ashraf H Wadaa ,  Rajshree Chabukswar ,  Ahmed Shams ,  Sze Ling Yeap ,  Refael Mizrahi ,  Nicholas Klein

IPC: G06F1/3234 ,  G06F11/30 ,  G06F9/50

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, a compute device to manage energy usage and compute performance includes at least one memory, instructions, and processor circuitry. The processor circuitry executes the instructions to determine a system power mode based on first telemetry data associated with the compute device. The processor circuitry executes the instructions to provide user activity data and second telemetry data associated with the compute device to a classification system. The processor circuitry executes the instructions to configure a plurality of parameters to manage power consumption and performance of the compute device based on a classification by the classification system.

公开(公告)号：US20220197367A1

公开(公告)日：2022-06-23

申请号：US17127899

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Deepak S Kirubakaran ,  Ramakrishnan Sivakumar ,  Russell Fenger ,  Monica Gupta ,  Jianwei Dai ,  Premanand Sakarda ,  Guy Therien ,  Rajshree Chabukswar ,  Chad Gutierrez ,  Renji Thomas

IPC: G06F1/3287 ,  G06F1/3228

Abstract: A hardware and software coordinated processor power state policy (e.g., policy for C-state) that delivers optimal power state selection by taking in to account the performance and/or responsiveness needs of thread expected to be scheduled on the core entering idle, to achieve improved IPC and performance for cores running user critical tasks. The scheme provides the ability to deliver responsiveness gains for important and/or user-critical threads running on a system-on-chip. A power management controller coupled to the plurality of processing cores, wherein the power management controller receives a hint from an operating system indicative of a bias towards a power state or performance state for at least one of the processing cores of the plurality of processing cores based on a priority of a thread in context switch.

公开(公告)号：US11093278B2

公开(公告)日：2021-08-17

申请号：US16605539

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Michael Chynoweth ,  Rajshree Chabukswar ,  Eliezer Weissmann ,  Jeremy Shrall

IPC: G06F9/48 ,  G06F1/324 ,  G06F9/32 ,  G06F9/50 ,  G06F11/07 ,  G06F11/30 ,  G06F11/34

Abstract: A processor includes processing engines, at least one performance counter, and a power control circuit. The at least one performance counter is to determine at least one interrupt rate metric for a first processing engine. The power control circuit is to determine, using the at least one performance counter, whether the at least one interrupt rate metric has reached a first threshold while the first processing engine is operating at a first frequency level, and in response to a determination that the at least one interrupt rate metric has reached the first threshold while the first processing engine is operating at the first frequency level, increase an operating frequency of the first processing engine from the first frequency level to a second frequency level.

公开(公告)号：US20210200656A1

公开(公告)日：2021-07-01

申请号：US16728617

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： ELIEZER WEISSMANN ,  Omer Barak ,  Rajshree Chabukswar ,  Russell Fenger ,  Eugene Gorbatov ,  Monica Gupta ,  Julius Mandelblat ,  Nir Misgav ,  Efraim Rotem ,  Ahmad Yasin

IPC: G06F11/34 ,  G06F9/48 ,  G06F15/80

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.

公开(公告)号：US20240045490A1

公开(公告)日：2024-02-08

申请号：US18449890

申请日：2023-08-15

Applicant: INTEL CORPORATION

Inventor： Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/329 ,  G06F1/3228 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F1/329 ,  G06F1/3228 ,  G06F9/3836 ,  G06F9/4812 ,  G06F9/4893

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

公开(公告)号：US11693588B2

公开(公告)日：2023-07-04

申请号：US15929272

申请日：2020-04-21

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Michael Chynoweth ,  Rajshree Chabukswar ,  Muhammad Taher

IPC: G06F3/06 ,  G06F11/34

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/3466

Abstract: A processor includes a memory subunit that includes a status register and an execution engine unit to: randomly select a load operation to monitor; determine a re-order buffer identifier of the load operation; and transmit the re-order buffer identifier to the memory subsystem. Responsive to receipt of the re-order buffer identifier, the first memory subunit is to store a piece of information, related to a status of the load operation, in the status register. The processor also includes logic to, responsive to detection of retirement of the load operation, store memory information in memory-related fields of a record of a memory buffer. The memory information includes auxiliary information (AUX) and access latency information, wherein one of the auxiliary information or the access latency information includes the piece of information, from the status register, stored in a particular field of the memory-related fields.

公开(公告)号：US11436118B2

公开(公告)日：2022-09-06

申请号：US16728617

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Omer Barak ,  Rajshree Chabukswar ,  Russell Fenger ,  Eugene Gorbatov ,  Monica Gupta ,  Julius Mandelblat ,  Nir Misgav ,  Efraim Rotem ,  Ahmad Yasin

IPC: G06F11/34 ,  G06F9/48 ,  G06F9/50 ,  G06F9/455 ,  G06F15/80

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.

公开(公告)号：US11422616B2

公开(公告)日：2022-08-23

申请号：US16830485

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/32 ,  G06F1/329 ,  G06F1/3228 ,  G06F9/38 ,  G06F9/48

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.