公开(公告)号：US10078356B2

公开(公告)日：2018-09-18

申请号：US14831768

申请日：2015-08-20

Applicant: Intel Corporation

Inventor： Vinit M. Abraham ,  Ramadass Nagarajan

IPC: G06F1/26 ,  G06F13/362

CPC classification number: G06F1/266 ,  G06F1/3287 ,  G06F13/362 ,  Y02D10/14 ,  Y02D10/171

Abstract: Described is an apparatus which comprises: an Intellectual Property (IP) block; control logic operable to send a first command to the IP block to cause the first IP block to enter a first power state from a second power state; and a communicating fabric coupled to the IP block and to the control logic, the communicating fabric to send multiple packets with a first header from the IP block to the control logic after the first command is processed by the IP block, wherein the multiple packets are associated with multiple registers which are identified as registers whose contents are to be saved.

公开(公告)号：US20180181432A1

公开(公告)日：2018-06-28

申请号：US15391984

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Robert De Gruijl ,  Sridhar Lakshmanamurthy ,  Ramadass Nagarajan ,  Peter J. Elardo

IPC: G06F9/46 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F9/467 ,  G06F13/4282 ,  G06F15/76 ,  G06F15/781 ,  G06F2213/0026

Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.

公开(公告)号：US09785223B2

公开(公告)日：2017-10-10

申请号：US14583151

申请日：2014-12-25

Applicant: Intel Corporation

Inventor： Ramadass Nagarajan ,  Jeremy J. Shrall ,  Erik G. Hallnor ,  Vinit Mathew Abraham ,  Ezra N. Harrington

IPC: G06F1/32 ,  G06F1/28

CPC classification number: G06F1/3287 ,  G06F1/28 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/171

Abstract: In an example, a shared uncore memory fabric of a system-on-a-chip (SoC) is configured to provide real-time power management. The SoC may include a power management agent to inform the shared fabric that the processing cores and peripherals will be idle for a time, and to negotiate a power-saving state. The uncore fabric may also include a local power manager that detects when no access requests have been received for a time, such as when cores are operating from cache. The shared fabric may then unilaterally enter a power-saving state, and remain in that state until an access request is received. In the power-saving state, power and/or clocks are gated, and the fabric's state is stored in retention cells. When a new access request is received, an ungated controller may handle preliminary processing while the local power manager restores the state and powers up the shared fabric.

公开(公告)号：US20160330033A1

公开(公告)日：2016-11-10

申请号：US15216317

申请日：2016-07-21

Applicant: INTEL CORPORATION

Inventor： Jorge E. Parra ,  Joydeep Ray ,  Ramadass Nagarajan

IPC: H04L9/32

CPC classification number: H04L9/3242 ,  G06F12/0607 ,  G06F13/16

Abstract: Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a general-purpose hashing function block that defines a default interleaving sequence for memory requests to alternately access the multiple memory channels and multiple specific-purpose hashing function blocks that define different interleaving sequences for the memory requests to alternately access the multiple memory channels. The MCU also includes a hashing-function selection block. The hashing-function selection block is operable to select one of the specific-purpose hashing function blocks or the general-purpose hashing function block for a current memory request in view of a requesting functional unit originating the current memory request.

Abstract translation: 描述了用于平衡多个存储器通道之间的存储器请求的动态异构散列函数技术。 处理器包括功能单元和多个存储器通道，以及耦合在它们之间的存储器控​​制器单元（MCU）。 MCU包括通用散列功能块，其定义用于交替访问多个存储器通道的存储器请求的默认交错序列，以及为存储器请求定义不同交错序列以交替访问多个存储器通道的多个特定目的散列功能块 。 MCU还包括散列函数选择块。 考虑到发起当前存储器请求的请求功能单元，散列函数选择块可操作用于选择用于当前存储器请求的特定目的散列功能块或通用散列功能块之一。

公开(公告)号：US09442864B2

公开(公告)日：2016-09-13

申请号：US14142117

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Uday R. Savagaonkar ,  Siddhartha Chhabra ,  Men Long ,  Alpa T. Narendra Trivedi ,  Carlos Ornelas ,  Edgar Borrayo ,  Ramadass Nagarajan ,  Stanley S. Kulick

IPC: G06F12/14 ,  G06F21/74

CPC classification number: G06F12/1408 ,  G06F12/1441 ,  G06F21/74 ,  G06F2212/1052

Abstract: A processor is described that includes one or more processing cores. The processor includes a memory controller to interface with a system memory having a protected region and a non protected region. The processor includes a protection engine to protect against active and passive attacks. The processor includes an encryption/decryption engine to protect against passive attacks. The protection engine includes bridge circuitry coupled between the memory controller and the one or more processing cores. The bridge circuitry is also coupled to the protection engine and the encryption/decryption engine. The bridge circuitry is to route first requests directed to the protected region to the protection engine and to route second requests directed to the non protected region to the encryption/decryption engine.

Abstract translation: 描述了包括一个或多个处理核心的处理器。 处理器包括与具有受保护区域和非保护区域的系统存储器接口的存储器控​​制器。 该处理器包括保护引擎，以防止主动和被动攻击。 该处理器包括一个加密/解密引擎，以防止被动攻击。 保护引擎包括耦合在存储器控制器和一个或多个处理核心之间的桥接电路。 桥接电路还耦合到保护引擎和加密/解密引擎。 桥接电路是将定向到保护区域的第一请求路由到保护引擎，并将定向到非保护区域的第二请求路由到加密/解密引擎。

公开(公告)号：US20160188469A1

公开(公告)日：2016-06-30

申请号：US14583611

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Ramadass Nagarajan ,  Jose S. Niell ,  Michael T. Klinglesmith ,  Derek T. Bachand ,  Ganesh Kumar

IPC: G06F12/08 ,  G06F13/42 ,  G06F13/28

CPC classification number: G06F12/0815 ,  G06F9/5016 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/084 ,  G06F13/287 ,  G06F13/4282 ,  G06F2212/1028 ,  G06F2212/154 ,  G06F2212/621

Abstract: In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the processors connects to shared resources such as memory and peripherals via a shared uncore fabric. Because each input bus for each core can include hundreds of data lines, the number of lines into the shared uncore fabric can become prohibitive. Thus, inputs from each core are multiplexed, such as in a two-to-one configuration. The multiplexing may be a non-blocking, queued (such as FIFO) multiplexing to ensure that all packets from all cores are delivered to the uncore fabric. In certain embodiment, some smaller input lines may be provided to the uncore fabric non-multiplexed, and returns (outputs) from the uncore fabric to the cores may also be non-multiplexed.

Abstract translation: 在一个示例中，片上系统包括多个多核处理器，例如用于八个总核的四个双核处理器。 每个处理器通过共享的无孔结构连接到诸如存储器和外围设备之类的共享资源。 因为每个核心的每个输入总线可以包含数百条数据线，所以共享的非空心结构中的行数可能变得过高。 因此，来自每个核的输入被复用，例如以二对一的配置。 多路复用可以是非阻塞排队（例如FIFO）复用，以确保来自所有核心的所有分组被传送到非空心结构。 在某些实施例中，可以向未多路复用的非空心结构提供一些较小的输入线，并且还可以将从非织造结构返回（输出）到芯的非多路复用。

公开(公告)号：US20220116322A1

公开(公告)日：2022-04-14

申请号：US17561121

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Abhishek Reddy Pamu ,  Lakshminarayana Pappu ,  David J. Harriman ,  Ramadass Nagarajan

IPC: H04L45/00 ,  G06F15/78

Abstract: An apparatus comprises a first tile comprising a first instance of a plurality of global endpoints and a first instance of a plurality of local networks comprising a plurality of local endpoints; and an interconnect network of the first tile to couple to an interconnect network of a second tile, the second tile comprising a second instance of the plurality of global endpoints and a second instance of the plurality of local networks comprising the plurality of local endpoints; wherein the interconnect network utilizes an address space comprising unique identifiers for the plurality of global endpoints of the first and second tiles; and non-unique identifiers for the plurality of local endpoints of the first and second tiles, wherein non-unique identifiers are reused in multiple local networks of the plurality of local networks of the first and second tiles.

公开(公告)号：US20210042147A1

公开(公告)日：2021-02-11

申请号：US17080970

申请日：2020-10-27

Applicant: Intel Corporation

Inventor： Robert P. Adler ,  Robert De Gruijl ,  Sridhar Lakshmanamurthy ,  Ramadass Nagarajan ,  Peter J. Elardo

IPC: G06F9/46 ,  G06F15/76 ,  G06F15/78 ,  G06F13/42

Abstract: In one embodiment, a system on chip includes a first endpoint to issue a non-posted memory write transaction to a memory and a Peripheral Component Interconnect (PCI)-based fabric including control logic to direct the non-posted memory write transaction to the memory, receive a completion for the non-posted memory write transaction from the memory and route the completion to the first endpoint. Other embodiments are described and claimed.

公开(公告)号：US09680652B2

公开(公告)日：2017-06-13

申请号：US15216317

申请日：2016-07-21

Applicant: INTEL CORPORATION

Inventor： Jorge E. Parra ,  Joydeep Ray ,  Ramadass Nagarajan

IPC: H04L9/32 ,  G06F13/16 ,  G06F12/06

CPC classification number: H04L9/3242 ,  G06F12/0607 ,  G06F13/16

Abstract: Dynamic heterogeneous hashing function technology for balancing memory requests between multiple memory channels is described. A processor includes functional units and multiple memory channels, and a memory controller unit (MCU) coupled between them. The MCU includes a general-purpose hashing function block that defines a default interleaving sequence for memory requests to alternately access the multiple memory channels and multiple specific-purpose hashing function blocks that define different interleaving sequences for the memory requests to alternately access the multiple memory channels. The MCU also includes a hashing-function selection block. The hashing-function selection block is operable to select one of the specific-purpose hashing function blocks or the general-purpose hashing function block for a current memory request in view of a requesting functional unit originating the current memory request.

公开(公告)号：US20170052579A1

公开(公告)日：2017-02-23

申请号：US14831768

申请日：2015-08-20

Applicant: Intel Corporation

Inventor： Vinit M. Abraham ,  Ramadass Nagarajan

IPC: G06F1/26 ,  G06F13/362

CPC classification number: G06F1/266 ,  G06F13/362 ,  Y02D10/14

Abstract: Described is an apparatus which comprises: an Intellectual Property (IP) block; control logic operable to send a first command to the IP block to cause the first IP block to enter a first power state from a second power state; and a communicating fabric coupled to the IP block and to the control logic, the communicating fabric to send multiple packets with a first header from the IP block to the control logic after the first command is processed by the IP block, wherein the multiple packets are associated with multiple registers which are identified as registers whose contents are to be saved.

Abstract translation: 描述了一种装置，其包括：知识产权（IP）块; 控制逻辑可操作以向所述IP块发送第一命令以使所述第一IP块从第二功率状态进入第一功率状态; 以及耦合到所述IP块和所述控制逻辑的通信结构，所述通信结构在所述IP块处理所述第一命令之后，将具有第一报头的多个分组从所述IP块发送到所述控制逻辑，其中所述多个分组是 与被标识为要保存其内容的寄存器的多个寄存器相关联。