公开(公告)号：US20240126695A1

公开(公告)日：2024-04-18

申请号：US18392310

申请日：2023-12-21

Applicant: Intel Corporation

Inventor： Yao Zu DONG ,  Kun TIAN ,  Fengguang WU ,  Jingqi LIU

IPC: G06F12/0802 ,  G06F3/06

CPC classification number: G06F12/0802 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0667 ,  G06F3/0673 ,  G06F2212/651

Abstract: Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.

公开(公告)号：US20190220301A1

公开(公告)日：2019-07-18

申请号：US16328062

申请日：2016-09-26

Applicant: INTEL CORPORATION

Inventor： Xiao ZHENG ,  Yao Zu DONG ,  Kun TIAN

IPC: G06F9/455 ,  G06F12/02

CPC classification number: G06F9/45558 ,  G06F12/0292 ,  G06F12/1009 ,  G06F2009/45583 ,  G06F2212/151 ,  G06F2212/50 ,  G06F2212/651 ,  G06F2212/657

Abstract: An apparatus and method are described for implementing a hybrid layer of address mapping for an IOMMU implementation. For example, one embodiment of a graphics processing apparatus comprises: virtualization circuitry to implement a virtualized execution environment in which a plurality of guest virtual machines (VMs) are to execute and share execution resources of the graphics processing apparatus; an input/output (I/O) memory management unit (IOMMU) to couple the VMs to one or more I/O devices; a hybrid layer address mapping (HLAM) module to combine entries from a per-process graphics translation table (PPGTT) with entries from a global graphics translation table (GGTT) into a first integrated page table, the first integrated page table mapping PPGTT guest page numbers (GPNs) to host page numbers (HPNs) and mapping GGTT virtual GPNs to HPNs; the HLAM to transform a GGTT GPN into a virtual GPN usable to access a corresponding HPN within the first integrated page table in response to a GGTT read/write operation generated by a first guest virtual machine (VM).

公开(公告)号：US20180122039A1

公开(公告)日：2018-05-03

申请号：US15553143

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Yao Zu DONG ,  Zhi WANG

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/48 ,  G06F12/1027 ,  G06F12/1009 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06F8/427 ,  G06F8/44 ,  G06F9/45512 ,  G06F9/45558 ,  G06F9/4843 ,  G06F9/4881 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2009/45583 ,  G06F2212/302 ,  G06F2212/657 ,  G06T1/60 ,  G06T15/005

Abstract: An apparatus may include a graphics processing unit (GPU) and a hypervisor. The hypervisor may include a command parser to parse graphics memory addresses associated with a workload of a virtual machine of the apparatus, and generate a first shadow global graphics translation table (SGGT) for translating the graphics memory addresses. The hypervisor may further include a GPU scheduler to check conflict between the first SGGTT and a second SGGTT containing graphics memory addresses used by working sets being-executed or to-be-executed by the render engines of the GPU, and schedule the workload of the virtual machine to a render engine when there is no conflict between the first SGGTT and the second SGGTT. Other embodiments may be described and/or claimed.

公开(公告)号：US20180024855A1

公开(公告)日：2018-01-25

申请号：US15633497

申请日：2017-06-26

Applicant: Intel Corporation

Inventor： Yao Zu DONG ,  Zhiyuan LV

IPC: G06F9/455 ,  G06T1/20 ,  G06F9/445 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F9/445 ,  G06F9/4856 ,  G06F9/50 ,  G06F9/5077 ,  G06F2009/4557 ,  G06F2009/45583 ,  G06F2209/501 ,  G06T1/20 ,  G06T2200/28

Abstract: Apparatuses, methods and storage medium associated with live migration of VMs from/to host computers with graphics virtualization are disclosed herein. In embodiments, an apparatus may include a VMM having a memory manager to manage accesses of system memory of the apparatus, including tracking of modified memory pages of the system memory. Additionally, the VMM may include a graphics command parser to analyze graphics commands issued to a GPU of the apparatus to detect writes to the system memory caused by the graphics commands, and augment the tracking of modified memory pages. Further, the VMM may include a live migration function to live migrate a VM to another apparatus, including provision of current memory content of the VM, utilizing modified memory pages tracked by the memory manager, as augmented by the graphics command parser. Other embodiments may be described and/or claimed.

公开(公告)号：US20160299773A1

公开(公告)日：2016-10-13

申请号：US14777316

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Yao Zu DONG ,  Zhiyuan LV

IPC: G06F9/455 ,  G06T1/20

CPC classification number: G06F9/45558 ,  G06F9/445 ,  G06F9/4856 ,  G06F9/50 ,  G06F9/5077 ,  G06F2009/4557 ,  G06F2009/45583 ,  G06F2209/501 ,  G06T1/20 ,  G06T2200/28

Abstract: Apparatuses, methods and storage medium associated with live migration of VMs from/to host computers with graphics virtualization are disclosed herein. In embodiments, an apparatus may include a VMM having a memory manager to manage accesses of system memory of the apparatus, including tracking of modified memory pages of the system memory. Additionally, the VMM may include a graphics command parser to analyze graphics commands issued to a GPU of the apparatus to detect writes to the system memory caused by the graphics commands, and augment the tracking of modified memory pages. Further, the VMM may include a live migration function to live migrate a VM to another apparatus, including provision of current memory content of the VM, utilizing modified memory pages tracked by the memory manager, as augmented by the graphics command parser. Other embodiments may be described and/or claimed.

Abstract translation: 本文公开了与从虚拟机到具有图形虚拟化的主计算机的实时迁移相关联的装置，方法和存储介质。 在实施例中，设备可以包括具有存储器管理器以管理设备的系统存储器的访问的VMM，包括跟踪系统存储器的修改的存储器页面。 此外，VMM可以包括图形命令解析器，以分析发布到装置的GPU的图形命令，以检测由图形命令引起的对系统存储器的写入，并且增加修改的存储器页面的跟踪。 此外，VMM可以包括实时迁移功能，以将VM迁移到另一设备，包括利用由图形命令解析器增强的由存储器管理器跟踪的修改的存储器页面提供VM的当前存储器内容。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20160203012A1

公开(公告)日：2016-07-14

申请号：US14776627

申请日：2014-06-24

Applicant: Yao Zu DONG ,  Xiantao ZHANG, ,  INTEL CORPORATION

Inventor： Yao Zu DONG ,  Xiantao ZHANG

IPC: G06F9/455 ,  G06F1/32 ,  G06F9/48

CPC classification number: G06F9/45533 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  G06F9/455 ,  G06F9/45558 ,  G06F9/48 ,  G06F9/4893 ,  G06F2009/45575 ,  G06F2009/45591 ,  Y02D10/24

Abstract: Embodiments described herein relate generally to managing the power consumption of a virtual machine on a computing device. The computing device may include a virtual machine power management feature that is to detect when a virtual machine running on the computing device should be frozen. In response to this detection, the virtual machine may be frozen by reducing the processor cycles consumed by the virtual machine. This detection may be based on, for example, detection that the virtual machine is no longer running in the foreground or detection that the virtual machine is idle. The computing device may be a portable electronic device in which power consumption is an important consideration. Other embodiments may be described and/or claimed.

Abstract translation: 本文描述的实施例一般涉及管理计算设备上的虚拟机的功耗。 计算设备可以包括虚拟机电源管理功能，其将检测何时应该冻结在计算设备上运行的虚拟机。 响应于该检测，可以通过减少虚拟机消耗的处理器周期来冻结虚拟机。 该检测可以基于例如检测到虚拟机不再在前台运行或检测虚拟机空闲。 计算设备可以是其中功耗是重要考虑因素的便携式电子设备。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20190018747A1

公开(公告)日：2019-01-17

申请号：US16080234

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Yao Zu DONG ,  Kun TIAN

IPC: G06F11/22 ,  G06F11/14

CPC classification number: G06F11/2236 ,  G06F11/14 ,  G06F11/1469 ,  G06F11/3024 ,  G06F11/3447 ,  G06F11/3476 ,  G06F2201/815 ,  G06F2201/84

Abstract: An apparatus and method performing debug and rollback operations using snapshots. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) to perform graphics processing operations by executing graphics commands; a command parser to parse graphics commands submitted to the GPU and generate a list of graphics memory pages which will be affected by the graphics commands; an I/O state tracker to track I/O accesses from a graphics driver to determine a list of registers affected by the I/O accesses; shapshot circuitry and/or logic to perform a memory snapshot and I/O snapshot based on the list of graphics memory pages and the list of registers, respectively; and rollback circuitry and/or logic to perform a rollback operation using the memory snapshot and I/O snapshot in response to detecting a GPU error condition.

公开(公告)号：US20180374187A1

公开(公告)日：2018-12-27

申请号：US16062511

申请日：2015-12-22

Applicant: INTEL CORPORATION

Inventor： Yao Zu DONG ,  Kun TIAN ,  Tian ZHANG ,  Yulei ZHANG

IPC: G06T1/20 ,  G06F9/48

Abstract: An apparatus and method for best effort quality of service scheduling in a graphics processing architecture. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) to perform graphics processing operations for a plurality of guests; a plurality of buffers to store one or more graphics commands associated with each guest to be executed by the GPU; and a scheduler to evaluate commands in the buffers of a first guest to estimate a cost of executing the commands, the scheduler to select all or a subset of the buffers of the first guest for execution on the GPU based on a determination that the selected buffers can be executed by the GPU within a remaining time slice allocated to the first guest.

公开(公告)号：US20180349162A1

公开(公告)日：2018-12-06

申请号：US15576835

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Kun TIAN ,  Yao Zu DONG

IPC: G06F9/455 ,  G06F9/54 ,  G06F12/10

CPC classification number: G06F9/45558 ,  G06F9/544 ,  G06F12/10 ,  G06F12/1009 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/657

Abstract: An apparatus and method are described for efficient inter-virtual machine (VM) communication. For example, an apparatus comprises inter-VM communication logic to map a first specified set of device virtual memory addresses of a first VM to a first set of physical memory addresses in a shared system memory and to further map a second specified set of device virtual memory addresses of a second VM to the first set physical memory addresses in the shared system memory.

公开(公告)号：US20180210840A1

公开(公告)日：2018-07-26

申请号：US15815511

申请日：2017-11-16

Applicant: Intel Corporation

Inventor： Yao Zu DONG ,  Kun TIAN

IPC: G06F12/109 ,  G06F9/50 ,  G06F12/02 ,  G06F9/455 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus and method are described for managing a virtual graphics processor unit (GPU). For example, one embodiment of an apparatus comprises: a dynamic addressing module to map portions of an address space required by the virtual machine to matching free address spaces of a host if such matching free address spaces are available, and to select non-matching address spaces for those portions of the address space required by the virtual machine which cannot be matched with free address spaces of the host; and a balloon module to perform address space ballooning (ASB) techniques for those portions of the address space required by the virtual machine which have been mapped to matching address spaces of the host; and address remapping logic to perform address remapping techniques for those portions of the address space required by the virtual machine which have not been mapped to matching address spaces of the host.