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    SCALABLE AND INTEROPERABLE PHYLESS DIE-TO-DIE IO SOLUTION
    11.
    发明申请
    SCALABLE AND INTEROPERABLE PHYLESS DIE-TO-DIE IO SOLUTION 有权

    公开(公告)号：US20210398906A1

    公开(公告)日：2021-12-23

    申请号：US16910023

    申请日：2020-06-23

    Applicant: Intel Corporation

    Inventor： Zhiguo QIAN ,  Gerald PASDAST ,  Juan ZENG ,  Peipei WANG ,  Ahmad SIDDIQUI ,  Lakshmipriya SESHAN

    IPC: H01L23/538 ,  H01L23/00

    Abstract: Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.

    GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION
    12.
    发明申请
    GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION 审中-公开

    公开(公告)号：US20190333848A1

    公开(公告)日：2019-10-31

    申请号：US16509387

    申请日：2019-07-11

    Applicant: Intel Corporation

    Inventor： Zhiguo QIAN ,  Kemal AYGUN ,  Yu ZHANG

    IPC: H01L23/498

    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

    HORIZONTAL PITCH TRANSLATION USING EMBEDDED BRIDGE DIES
    17.
    发明申请
    HORIZONTAL PITCH TRANSLATION USING EMBEDDED BRIDGE DIES 有权

    公开(公告)号：US20220157706A1

    公开(公告)日：2022-05-19

    申请号：US17665315

    申请日：2022-02-04

    Applicant: Intel Corporation

    Inventor： Sujit SHARAN ,  Kemal AYGUN ,  Zhiguo QIAN ,  Yidnekachew MEKONNEN ,  Zhichao ZHANG ,  Jianyong XIE

    IPC: H01L23/498 ,  H01L23/00

    Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

    PACKAGE SUBSTRATES WITH MAGNETIC BUILD-UP LAYERS
    18.
    发明申请
    PACKAGE SUBSTRATES WITH MAGNETIC BUILD-UP LAYERS 审中-公开

    公开(公告)号：US20200373232A1

    公开(公告)日：2020-11-26

    申请号：US16993112

    申请日：2020-08-13

    Applicant: Intel Corporation

    Inventor： Zhiguo QIAN ,  Kaladhar RADHAKRISHNAN ,  Kemal AYGUN

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/68

    Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.

    OPTIMAL SIGNAL ROUTING PERFORMANCE THROUGH DIELECTRIC MATERIAL CONFIGURATION DESIGNS IN PACKAGE SUBSTRATE
    19.
    发明申请
    OPTIMAL SIGNAL ROUTING PERFORMANCE THROUGH DIELECTRIC MATERIAL CONFIGURATION DESIGNS IN PACKAGE SUBSTRATE 审中-公开

    公开(公告)号：US20200343175A1

    公开(公告)日：2020-10-29

    申请号：US16392171

    申请日：2019-04-23

    Applicant: Intel Corporation

    Inventor： Zhiguo QIAN ,  Gang DUAN ,  Kemal AYGÜN ,  Jieying KONG

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/66

    Abstract: Embodiments include package substrates and methods of forming the package substrates. A package substrate includes a first conductive layer in a first dielectric, a second dielectric over the first dielectric, and a second conductive layer in the second dielectric, where the second conductive layer includes first and second traces. The package substrate also includes a third conductive layer over the second dielectric, and a high dielectric constant (Dk) and low DK regions in the first and second dielectrics, where the high Dk region surrounds the first traces, and where the low Dk region surrounds the second traces. The high Dk region may be between the first and third conductive layers. The low Dk region may be between the first and third conductive layers. The package substrate may include a dielectric region in the first and second dielectrics, where the dielectric region separates the high Dk and low Dk regions.

    INTEGRATED CIRCUIT PACKAGE WITH TEST CIRCUITRY FOR TESTING A CHANNEL BETWEEN DIES
    20.
    发明申请
    INTEGRATED CIRCUIT PACKAGE WITH TEST CIRCUITRY FOR TESTING A CHANNEL BETWEEN DIES 审中-公开

    公开(公告)号：US20190295953A1

    公开(公告)日：2019-09-26

    申请号：US15933934

    申请日：2018-03-23

    Applicant: Intel Corporation

    Inventor： Mayue XIE ,  Jong-Ru GUO ,  Zhiguo QIAN ,  Zuoguo WU

    IPC: H01L23/538 ,  H01L23/58 ,  H01L25/065

    Abstract: Apparatuses, systems and methods associated with integrated circuit packages with integrated test circuitry for testing of a channel between dies are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first die, a second die, and a channel that couples the first die to the second die. The first die may include a transmitter, test circuitry coupled between the transmitter and the channel, wherein the test circuitry is to control charge and discharge of the channel, and a receiver coupled to the channel. The receiver may determine a voltage of the channel during charge and discharge of the channel, and output an indication of the voltage. Other embodiments may be described and/or claimed.

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