Abstract:
A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.
Abstract:
A method, system, and computer program product for controlling power supplied to a processor is disclosed. A voltage regulator is set to a first voltage regulator set point, wherein the first voltage regulator set point provides a first load line for operation of the processor. A change in an operation of the processor from a first operating condition along the first load line to a second operating condition along the first load line is determined. The voltage regulator is the set to a second voltage regulator set point and the processor is operated at a third operating condition on a second load line corresponding to the second voltage regulator set point.
Abstract:
A method includes monitoring power usage for a storage system that includes a set storage units at a first level of storage granularity and a set of storage sub-units at a second level of storage granularity, wherein the second level of storage granularity is finer than the first level of storage granularity. The method further includes assigning a non-uniform power budget to the set of storage units and adjusting a power budget for the storage sub-units according to the non-uniform power budget assigned to the storage units. A corresponding computer program product and computer system are also disclosed herein.
Abstract:
A memory is provided that comprises a bank of non-volatile memory cells configured into a plurality of banklets. Each banklet in the plurality of banklets can be enabled separately and independently of the other banklets in the bank of non-volatile memory cells. The memory further comprises peripheral banklet circuitry, coupled to the bank of a non-volatile memory array, that is configured to enable selected subsets of bit lines within a selected banklet within the plurality of banklets. Moreover, the memory comprises banklet select circuitry, coupled to the peripheral banklet circuitry, that is configured to select data associated with a selected banklet for reading out from the banklet or writing to the banklet.
Abstract:
A mechanism is provided for implementing an operational parameter change within the data processing system based on an identified degradation. One or more degradations existing in the data processing system are identified based on a set of degradation values obtained from a set of degradation sensors. A determination is made as to whether one or more operational parameters need to be modified based on the one or more identified degradations. Responsive to determining that the one or more operational parameters need to be modified based on the one or more identified degradations, an input change is implemented to a one or more control devices in order that the one or more operational parameters are modified.
Abstract:
A mechanism is provided for determining a modeled age of a mufti-core processor. For each core in a set of cores in the multi-core processor, a determination is made of a temperature, a voltage, and a frequency at regular intervals for a set of degradations and a set of voltage domains, thereby forming the modeled age of the multi-core processor. A determination is made as to whether the modeled age of the multi-core processor is greater than an end-of-life value. Responsive to the modeled age of the multi-core processor being greater than an end-of-life value, an indication is sent that the multi-core processor requires replacement.
Abstract:
A sensor array including multiple current sensors provides input for power measurement and management systems. The sensor array includes split ferrite cylinder portions connected by a frame, so that when the array is installed around multiple branch circuits in a power distribution panel or raceway, the ferrite cylinders are completed to surround the conductor(s) of the associated branch circuit. Voltage sensing may also be incorporated within the sensors by providing an electrically conductive plate, wire or other element that capacitively couples to the corresponding wire(s).
Abstract:
A data center energy management (DCEM) server configures a power supply in the data center. The DCEM server sums input alternating current (AC) power of the power supply to a total AC power of the data center, wherein the total AC power of the data center is a sum of AC power of a plurality of power supplies. The DCEM server sums output direct current (DC) power of the power supply to a total DC power of the data center and reports a ratio of total AC power to total DC power as data center power conversion efficiency. The DCEM server sets a preset power supply efficiency threshold. The DCEM server determines that a real-time power efficiency level is below the power supply efficiency threshold. The DCEM server, responsive to a determination that real-time power efficiency level is below the power supply efficiency threshold, may remedy the power supply.
Abstract:
Computing system voltage control methods include receiving an indication of a first performance state. The first performance state is associated with a first voltage and applies to at least one computing system component. The indication of the first performance state is received by a first computing system component from a second computing system component. An indication of a second performance state is received, wherein the second performance state is associated with a second voltage that is not equal to the first voltage. It is determined whether the second performance state is within a range defined by a minimum performance state and a maximum performance state. Responsive to determining that the second performance state is within the range defined by the minimum performance state and the maximum performance state, the voltage of the at least one computing system component is set equal to the voltage associated with the second performance state.
Abstract:
A clamping current and voltage sensor provides an isolated and convenient technique for measuring current passing through a conductor such as an AC branch circuit wire, as well as providing an indication of an electrostatic potential on the wire, which can be used to indicate the phase of the voltage on the wire, and optionally a magnitude of the voltage. The device includes a body formed from two handle portions that contain the current and voltage sensors within an aperture at the distal end, which may be a ferrite cylinder with a hall effect sensor disposed in a gap along the circumference to measure current, or alternatively a winding provided through the cylinder along its axis and a capacitive plate or wire disposed adjacent to, or within, the ferrite cylinder to provide the indication of the voltage. When the handles are compressed the aperture is opened to permit insertion of a wire for measurement.