公开(公告)号：US20220293853A1

公开(公告)日：2022-09-15

申请号：US17198775

申请日：2021-03-11

Applicant: International Business Machines Corporation

Inventor： Praneet Adusumilli ,  Takashi Ando ,  REINALDO VEGA ,  Cheng Chi

IPC: H01L45/00 ,  G11C13/00

Abstract: A device includes an electronic component, and the electronic component includes a first pad, a second pad, and a strip connecting the first pad and the second pad. The device further includes a first electrode in contact with the first pad and a second electrode in contact with the second pad. The electronic component is made of a phase change material. At least one of the first electrode and the second electrode is coated with a material that is configured to increase a difference in workfunction between the first electrode and the second electrode.

公开(公告)号：US20200312912A1

公开(公告)日：2020-10-01

申请号：US16368065

申请日：2019-03-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： REINALDO VEGA ,  TAKASHI ANDO ,  HARI MALLELA ,  Li-Wen Hung

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A stacked resistive random access memory (ReRAM) structure is provided. The stacked ReRAM structure includes a channel, a ReRAM cell sub-structure and a contact via sub-structure. The ReRAM cell structure includes ReRAM cell, drain, gate and source layers, which are insulated from one another and respectively disposed in operative contact with the channel. The contact via sub-structures includes first, second, third and fourth contact vias, which are separate from one another. The first contact via is disposed in exclusive operative contact with the ReRAM cell layer. The second contact via is disposed in exclusive operative contact with the drain layer. The third contact via is disposed in exclusive operative contact with the gate layer. The fourth contact via is disposed in exclusive operative contact with the source layer.

公开(公告)号：US20240170392A1

公开(公告)日：2024-05-23

申请号：US17989932

申请日：2022-11-18

Applicant: International Business Machines Corporation

Inventor： REINALDO VEGA ,  Nicholas Anthony Lanzillo ,  Albert M. Chu ,  Lawrence A. Clevenger ,  Ruilong Xie ,  Brent A. Anderson

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L23/53209

Abstract: A structure is provided that includes a first metal level including a first metal line, a second metal level spaced apart from the first metal level and including a second metal line, and a first metal via structure connecting the first metal line to the second metal line. The first metal via structure directly contacts a sidewall surface and a horizontal surface of the first metal line.

公开(公告)号：US20240145311A1

公开(公告)日：2024-05-02

申请号：US17978942

申请日：2022-11-01

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  REINALDO VEGA ,  Albert M. Chu

IPC: H01L21/8234 ,  H01L23/528 ,  H01L23/535 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823418 ,  H01L23/5286 ,  H01L23/535 ,  H01L29/66666 ,  H01L29/7827

Abstract: A vertical transport field effect transistor (VTFET) apparatus includes a fin-shaped channel structure; a gate stack that surrounds the channel structure; a top source/drain structure at a top end of the channel structure; a top interconnect layer above the top source/drain structure; a top contact that electrically connects the top source/drain structure to the top interconnect layer; a bottom source/drain structure at a bottom end of the channel structure; a backside interconnect layer below the bottom source/drain structure; and a backside contact that touches a bottom surface of the bottom source/drain structure and also touches a side surface of the bottom source/drain structure and electrically connects the bottom source/drain structure to the backside interconnect layer.

公开(公告)号：US20240136414A1

公开(公告)日：2024-04-25

申请号：US18049297

申请日：2022-10-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Brent A. Anderson ,  REINALDO VEGA ,  Albert M. Chu ,  Lawrence A. Clevenger

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a semiconductor wafer having a first transistor and a second transistor; a first source/drain (S/D) contact of the first transistor; a second S/D contact of the second transistor; and a cut region between the first S/D contact and the second S/D contact, wherein the cut region includes a liner of a first dielectric material and a filler of a second dielectric material that is different from the first dielectric material, the liner lining at least a part of the first S/D contact and a part of the second S/D contact, and the filler being directly adjacent to the liner and between the first S/D contact and the second S/D contact. A method of manufacturing the semiconductor structure is also provided.

公开(公告)号：US20240105841A1

公开(公告)日：2024-03-28

申请号：US17936164

申请日：2022-09-28

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Albert M. Chu ,  Lawrence A. Clevenger ,  Ruilong Xie ,  Nicholas Anthony Lanzillo ,  REINALDO VEGA

IPC: H01L29/78 ,  H01L27/02 ,  H01L29/417

CPC classification number: H01L29/7827 ,  H01L27/0207 ,  H01L29/41741

Abstract: A vertical-transport field-effect transistor (VTFET) is on a wafer. The VTFET has a first width. The first width is a contacted poly pitch (CPP). A bottom source/drain region of the VTFET extends at least the first width from the VTFET. A contact from a frontside of the VTFET is connected to the bottom source/drain region.

公开(公告)号：US20230062819A1

公开(公告)日：2023-03-02

申请号：US17463704

申请日：2021-09-01

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Jingyun Zhang ,  REINALDO VEGA ,  Kangguo Cheng

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L21/265 ,  H01L21/8238 ,  H01L29/66

Abstract: A CFET includes a fin that has a bottom channel portion, a top channel portion, and a channel isolator between the bottom channel portion and the top channel portion. The CFET further includes a source and drain stack that has a bottom source or drain (S/D) region connected to the bottom channel portion, a top S/D region connected to the top channel portion, a source-drain isolator between the bottom S/D region and the top S/D region. The CFET further includes a spacer foot physically connected to a base sidewall portion of the bottom S/D region and a buried S/D contact that is physically connected to an upper sidewall portion of the bottom S/D region. The CFET may further include a common gate around the bottom channel portion, around the top channel portion, and around the channel isolator.

公开(公告)号：US20230041159A1

公开(公告)日：2023-02-09

申请号：US17397068

申请日：2021-08-09

Applicant: International Business Machines Corporation

Inventor： Jingyun Zhang ,  REINALDO VEGA ,  MIAOMIAO WANG ,  Takashi Ando

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A nanosheet semiconductor device includes a first ferroelectric region between a channel nanosheet stack and a gate contact. The channel nanosheet stack includes a plurality of channel nanosheets each connected to a source and connected to a drain and a gate surrounding the plurality of channel nanosheets and connected to the source and connected to the drain. The nanosheet semiconductor device may further include a second ferroelectric region upon a sidewall of the channel nanosheet stack. Sidewalls of the first ferroelectric region may be substantially coplanar with or inset from underlying sidewalls of the channel nanosheet stack.

公开(公告)号：US20220190167A1

公开(公告)日：2022-06-16

申请号：US17118752

申请日：2020-12-11

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  REINALDO VEGA ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L27/07

Abstract: A negative capacitance field effect transistor (NCFET) device is provided. The NCFET device includes a substrate, and a transistor stack structure formed on the substrate. The nanosheet stack structure includes a PFET region and an NFET region, the PFET region including a pWF metal layer stack and the NFET region including a nWF metal layer stack. The NCFET device also includes a dielectric interfacial layer formed on the transistor stack structure, the dielectric interfacial layer including metal induced oxygen vacancies, and the dielectric interfacial layer formed on a portion of the transistor stack structure. The NCFET device also includes a top electrode formed on the dielectric interfacial layer.

公开(公告)号：US20220158091A1

公开(公告)日：2022-05-19

申请号：US16952203

申请日：2020-11-19

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Praneet Adusumilli ,  REINALDO VEGA ,  Cheng Chi

IPC: H01L45/00 ,  H01L27/24 ,  G06N3/04 ,  G06N3/063

Abstract: A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a first electrode, a first resistive structure in contact with the first electrode, a dielectric layer in contact with the first resistive structure, and a second resistive structure in contact with the dielectric layer. The second resistive structure includes a resistive material layer and a high work function metal core. The ReRAM device also includes a second electrode in contact with the second resistive structure.