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公开(公告)号:US10665635B1
公开(公告)日:2020-05-26
申请号:US16395061
申请日:2019-04-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Martin O. Sandberg , Sami Rosenblatt , Rasit O. Topaloglu
Abstract: A tunable qubit device includes a tunable qubit, the tunable qubit including a superconducting quantum interference device (SQUID) loop. The tunable qubit device further includes a superconducting loop inductively coupled to the SQUID loop, and a flux bias line inductively coupled to the superconducting loop. The superconducting loop includes a superconducting material having a critical temperature that is a lower temperature than a critical temperature of any superconducting material of the tunable qubit. In operation, the superconducting loop provides a persistent bias to the tunable qubit.
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公开(公告)号:US20200152853A1
公开(公告)日:2020-05-14
申请号:US16591993
申请日:2019-10-03
Applicant: International Business Machines Corporation
Inventor: Sami Rosenblatt , Rasit Onur Topaloglu
Abstract: Systems and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter, transmitter, and/or antenna can be positioned above a superconducting qubit chip having a Josephson junction coupled to a set of one or more capacitor pads. The radio frequency emitter, transmitter, and/or antenna can emit an electromagnetic signal onto the set of one or more capacitor pads. The capacitor pads can function as receiving antennas and therefore receive the electromagnetic signal. Upon receipt of the electromagnetic signal, an alternating current and/or voltage can be induced in the capacitor pads, which current and/or voltage thereby heat the pads and the Josephson junction. The heating of the Josephson junction can change its physical properties, thereby annealing the Josephson junction. In another example, the emitter can direct the electromagnetic signal to avoid unwanted annealing of neighboring qubits on the superconducting qubit chip.
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公开(公告)号:US20200075833A1
公开(公告)日:2020-03-05
申请号:US16115001
申请日:2018-08-28
Applicant: International Business Machines Corporation
Inventor: Rasit Onur Topaloglu , Sami Rosenblatt
Abstract: Systems, computer-implemented methods, and techniques facilitating antenna-based thermal annealing of qubits are provided. In one example, a first antenna can be positioned above a superconducting qubit chip having a first Josephson junction and a second Josephson junction. The first antenna can direct a first electromagnetic wave toward the first Josephson junction. A first length of a first defined vertical gap, between the first antenna and the superconducting qubit chip, can be sized to cause the first electromagnetic wave to circumscribe a first set of one or more capacitor pads of the first Josephson junction, thereby annealing the first Josephson junction, without annealing the second Josephson junction. In another example, the first length of the first defined vertical gap can be a function of a model of the first electromagnetic wave as a cone, wherein the cone originates from the first antenna and extends toward the superconducting qubit chip.
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公开(公告)号:US10551254B2
公开(公告)日:2020-02-04
申请号:US15927224
申请日:2018-03-21
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Chandrasekara Kothandaraman , Sami Rosenblatt , Akil K. Sutton
Abstract: A ring oscillator system for characterizing substrate strain including, a substrate including a through-substrate-via, at least two ring oscillators, wherein a first ring oscillator is closer to the through-substrate-via than a second ring oscillator, and a logic difference circuit that is configured to receive an input from at least the first ring oscillator and the second ring oscillator, and detect a difference between the signal frequency of the first ring oscillator and the signal frequency of the second ring oscillator.
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公开(公告)号:US10367134B2
公开(公告)日:2019-07-30
申请号:US15616193
申请日:2017-06-07
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Markus Brink , Sami Rosenblatt
Abstract: A technique relates to forming a sidewall tunnel junction. A first conducting layer is formed using a first shadow mask evaporation. A second conducting layer is formed on a portion of the first conducting layer, where the second conducting layer is formed using a second shadow mask evaporation. An oxide layer is formed on the first conducting layer and the second conducting layer. A third conducting layer is formed on part of the oxide layer, such that the sidewall tunnel junction is positioned between the first conducting layer and the third conducting layer.
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公开(公告)号:US10305015B1
公开(公告)日:2019-05-28
申请号:US15827718
申请日:2017-11-30
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Markus Brink , Antonio Corcoles-Gonzalez , Jay M. Gambetta , Sami Rosenblatt , Firat Solgun
IPC: H01L39/22 , G06N99/00 , H01L39/24 , H01P3/08 , H01L25/065
Abstract: A technique relates to a structure. A first surface includes an inductive element of a resonator. A second surface includes a first portion of a capacitive element of the resonator and at least one qubit. A second portion of the capacitive element of the resonator is on the first surface.
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公开(公告)号:US20190051810A1
公开(公告)日:2019-02-14
申请号:US16153866
申请日:2018-10-08
Applicant: International Business Machines Corporation
Inventor: Markus Brink , Jared B. Hertzberg , Sami Rosenblatt
Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.
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公开(公告)号:US20190006284A1
公开(公告)日:2019-01-03
申请号:US15598928
申请日:2017-05-18
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Markus Brink , Jared B. Hertzberg , Sami Rosenblatt
Abstract: A technique relates to a superconducting chip. Resonant units have resonant frequencies, and the resonant units are configured as superconducting resonators. Josephson junctions are in the resonant units, and one or more of the Josephson junctions have a shorted tunnel barrier.
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公开(公告)号:US20180301450A1
公开(公告)日:2018-10-18
申请号:US15862976
申请日:2018-01-05
Applicant: International Business machines Corporation
Inventor: Sami Rosenblatt , Rasit O. Topaloglu
IPC: H01L27/088 , H01L29/06 , H01L21/762 , H01L21/82 , H01L21/3105 , H01L21/02 , H01L29/165 , H01L29/51 , H01L29/16 , H01L21/8238 , H01L21/8234
CPC classification number: H01L27/0886 , H01L21/02378 , H01L21/02527 , H01L21/31055 , H01L21/76224 , H01L21/8213 , H01L21/823431 , H01L21/823871 , H01L29/0649 , H01L29/1606 , H01L29/1608 , H01L29/165 , H01L29/517 , H01L29/7851
Abstract: A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.
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公开(公告)号:US20180301449A1
公开(公告)日:2018-10-18
申请号:US15799286
申请日:2017-10-31
Applicant: International Business Machines Corporation
Inventor: Sami Rosenblatt , Rasit O. Topaloglu
IPC: H01L27/088 , H01L29/51 , H01L29/165 , H01L29/16 , H01L29/06 , H01L21/02 , H01L21/8234 , H01L21/82 , H01L21/762 , H01L21/3105 , H01L21/8238
Abstract: A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed only upon the sidewalls of the fins.
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