公开(公告)号：US10665635B1

公开(公告)日：2020-05-26

申请号：US16395061

申请日：2019-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Martin O. Sandberg ,  Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L27/18 ,  H01L39/24 ,  H03K19/195 ,  G06N10/00 ,  H01L39/02 ,  H01L39/22 ,  H01L39/12 ,  H01L39/08

Abstract: A tunable qubit device includes a tunable qubit, the tunable qubit including a superconducting quantum interference device (SQUID) loop. The tunable qubit device further includes a superconducting loop inductively coupled to the SQUID loop, and a flux bias line inductively coupled to the superconducting loop. The superconducting loop includes a superconducting material having a critical temperature that is a lower temperature than a critical temperature of any superconducting material of the tunable qubit. In operation, the superconducting loop provides a persistent bias to the tunable qubit.

公开(公告)号：US20190138681A1

公开(公告)日：2019-05-09

申请号：US15805178

申请日：2017-11-07

Applicant: International Business Machines Corporation

Inventor： Rasit O. Topaloglu

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G06F17/5068 ,  G03F1/36 ,  G06F2217/02 ,  G06F2217/12

Abstract: An approach for shifting a cut associated with a lineend of an interconnect in a manufacturing system. The approach selects one or more polygons associated with a lineend and determines whether a first cut is spanning the one or more polygons. The approach responds to the first cut does span, determines a presence of a first via on a first interconnect and determines a first distance of the first via to the first cut. The approach determines whether the first distance is greater than a first threshold and responds to the first distance is greater and determines whether the first distance is greater and determines a second distance of the first cut to a second cut. The approach determines whether the second distance is greater than the second threshold and responds to the second distance is greater and generates a shift associated with the first cut and outputs the shift.

公开(公告)号：US10169525B2

公开(公告)日：2019-01-01

申请号：US15619004

申请日：2017-06-09

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Vincent J. McGahay ,  Rasit O. Topaloglu

IPC: G06F17/00 ,  G06F17/50 ,  H01L21/768 ,  H01L21/67 ,  G03F7/20 ,  H01L21/311

Abstract: A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire.

公开(公告)号：US20180301450A1

公开(公告)日：2018-10-18

申请号：US15862976

申请日：2018-01-05

Applicant: International Business machines Corporation

Inventor： Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L21/82 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/165 ,  H01L29/51 ,  H01L29/16 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/02378 ,  H01L21/02527 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/8213 ,  H01L21/823431 ,  H01L21/823871 ,  H01L29/0649 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/517 ,  H01L29/7851

Abstract: A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.

公开(公告)号：US20180301449A1

公开(公告)日：2018-10-18

申请号：US15799286

申请日：2017-10-31

Applicant: International Business Machines Corporation

Inventor： Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L27/088 ,  H01L29/51 ,  H01L29/165 ,  H01L29/16 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/82 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/8238

Abstract: A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed only upon the sidewalls of the fins.

公开(公告)号：US09601367B2

公开(公告)日：2017-03-21

申请号：US13849796

申请日：2013-03-25

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A design layout is provided such that an underlying conductive line structure underlies a stitch region in an overlying conductive line structure. A stitch-induced via structure can be formed between the underlying conductive line structure and the overlying conductive line structure when a stitch region in a hard mask layer is etched multiple times. At least one of the underlying conductive line structure and the overlying conductive line structure is electrically isolated from other conductive line structures in a same design level so as to avoid unintentional electrical shorts.

公开(公告)号：US20160378904A1

公开(公告)日：2016-12-29

申请号：US14753344

申请日：2015-06-29

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/70433 ,  G03F7/705 ,  G03F7/70633

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer.

Abstract translation: 各种实施例包括计算机实现的方法，用于分析表示用于叠加效果的集成电路（IC）的布局中的至少一个特征的计算机程序产品和系统。 在一些情况下，方法包括计算机实现的方法，包括：通过在形成表示IC之后的数据文件上运行化学机械抛光（CMP）模型，沉积模型或蚀刻模型中的至少一个来对IC的形貌进行建模 的最上层; 使用IC的地形模型对IC中的至少一个特征进行建模以获得覆盖效果; 以及响应于检测到所述至少一个特征中的覆盖效应，修改在形成最上层之后表示IC的数据文件，所述覆盖效应出现在最上层下面的层中。

公开(公告)号：US11487508B2

公开(公告)日：2022-11-01

申请号：US16383879

申请日：2019-04-15

Applicant: International Business Machines Corporation

Inventor： Rasit O. Topaloglu ,  Jonathan Z. Sun ,  Matthias G. Gottwald ,  Chandrasekharan Kothandaraman

IPC: G06F7/58 ,  H01L43/12 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

Abstract: A true random number generator (TRNG) device having a magnetic tunnel junction (MTJ) structure coupled to a domain wall wire. The MTJ structure is formed of a free layer (FL) and a reference layer (RL) that sandwiches a tunnel barrier layer. The free layer has anisotropy energy sufficiently low to provide stochastic fluctuation in the orientation of the magnetic state of the free layer via thermal energy. The domain wall wire is coupled to the MTJ structure. The domain wall wire has a domain wall. Movement of the domain wall tunes a probability distribution of the fluctuation in the orientation of the magnetic state of the free layer. The domain wall can be moved by application of a suitable current through the wire to tune the probability distribution of 1's and 0's generated by a readout circuit of the TRNG device.

公开(公告)号：US20190165237A1

公开(公告)日：2019-05-30

申请号：US15822338

申请日：2017-11-27

Applicant: International Business Machines Corporation

Inventor： Jared Barney Hertzberg ,  Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L39/02 ,  H01L23/48 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3205 ,  H01L39/24 ,  H01L39/22 ,  H03K19/195 ,  G06N99/00

CPC classification number: H01L39/025 ,  G06N10/00 ,  H01L21/32058 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53285 ,  H01L23/5329 ,  H01L27/18 ,  H01L39/223 ,  H01L39/2493 ,  H03K19/195

Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.

公开(公告)号：US10152567B2

公开(公告)日：2018-12-11

申请号：US15862782

申请日：2018-01-05

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

IPC: G06F17/50 ,  G03F7/20

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer.